Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2018/0005913 Package Device
Provided is a package device, relating to the technical field of lamp beads. The package device comprises an SMD holder, wherein the SMD holder is a hollow...
2018/0005912 WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The...
2018/0005903 SEMICONDUCTOR DEVICE INCLUDING DUAL TRENCH EPITAXIAL DUAL-LINER CONTACTS
A complementary metal-oxide-semiconductor field-effect transistor (CMOS) device includes a first source/drain (S/D) region and a second S/D region different...
2018/0005897 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of...
2018/0005894 SEMICONDUCTOR STRUCTURE HAVING CONTACT HOLES BETWEEN SIDEWALL SPACERS
The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality...
2018/0005891 INTEGRATED METAL GATE CMOS DEVICES
A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second...
2018/0005889 METHOD FOR COLLECTIVE (WAFER-SCALE) FABRICATION OF ELECTRONIC DEVICES AND ELECTRONIC DEVICE
Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate...
2018/0005888 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP
The present disclosure provides a semiconductor device including: a semiconductor chip including a circuit having a predetermined function, at least one first...
2018/0005887 THROUGH-SILICON VIA WITH INJECTION MOLDED FILL
Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along...
2018/0005886 CONTACT STRUCTURE AND ASSOCIATED METHOD FOR FLASH MEMORY
A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate...
2018/0005883 LOCATION-SPECIFIC LASER ANNEALING TO IMPROVE INTERCONNECT MICROSTRUCTURE
A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a...
2018/0005882 LOW-K DIELECTRIC INTERCONNECT SYSTEMS
A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric...
2018/0005881 METHODS OF ENHANCING POLYMER ADHESION TO COPPER
A method of processing a semiconductor substrate includes: immersing a substrate in a first bath, wherein the substrate comprises a barrier layer, a conductive...
2018/0005879 VIA AND TRENCH FILLING USING INJECTION MOLDED SOLDERING
A method includes forming one or more vias in a substrate, forming at least one liner on at least one sidewall of at least one of the vias, and filling said at...
2018/0005875 SELF-ALIGNED PATTERN FORMATION FOR A SEMICONDUCTOR DEVICE
A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of...
2018/0005874 VIA CLEANING TO REDUCE RESISTANCE
A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via...
2018/0005868 SELF-ALIGNED AIRGAPS WITH CONDUCTIVE LINES AND VIAS
A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric...
2018/0005867 ESC CERAMIC SIDEWALL MODIFICATION FOR PARTICLE AND METALS PERFORMANCE ENHANCEMENTS
A substrate support for a substrate processing system includes a baseplate and a ceramic layer arranged on the baseplate. The ceramic layer includes a lower...
2018/0005865 END EFFECTOR ASSEMBLY FOR CLEAN/DIRTY SUBSTRATE HANDLING
An end effector includes a body, a first tine, and a second tine. The body includes first, second, and third substrate support pads, the first substrate...
2018/0005864 USE OF VACUUM CHUCKS TO HOLD A WAFER OR WAFER SUB-STACK
Techniques are described for holding a wafer or wafer sub-stack to facilitate further processing of the wafer of sub-stack. In some implementations, a wafer or...
2018/0005860 ELECTROSTATIC CHUCK
An electrostatic chuck includes a dielectric layer and a conductive layer located inside the dielectric layer. The dielectric layer includes an upper surface...
2018/0005859 METHOD FOR REDUCING TEMPERATURE TRANSITION IN AN ELECTROSTATIC CHUCK
A method for controlling a substrate temperature in a substrate processing system includes determining a temperature difference between the substrate...
2018/0005857 SYSTEM AND METHOD FOR SUBSTRATE SUPPORT FEED-FORWARD TEMPERATURE CONTROL BASED ON RF POWER
A temperature controller is provided and includes interfaces, a compensation controller, summers, and a second controller. An interface receives a bias power...
2018/0005852 ION TO NEUTRAL CONTROL FOR WAFER PROCESSING WITH DUAL PLASMA SOURCE REACTOR
The disclosed techniques relate to methods and apparatus for etching a substrate. A plate assembly divides a reaction chamber into a lower and upper...
2018/0005850 SELECTIVE ETCH USING MATERIAL MODIFICATION AND RF PULSING
Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The...
2018/0005848 LIGHT-IRRADIATION HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS
A heat treatment apparatus is provided with two cool chambers, that is, a first cool chamber and a second cool chamber. A semiconductor wafer before treatment...
2018/0005847 CARRIER SUBSTRATES FOR SEMICONDUCTOR PROCESSING
A carrier substrate includes a base layer having a first surface, and having a second surface that is parallel to and opposite of the first surface. The...
2018/0005845 PACKING METHOD FOR SEMICONDUCTOR DEVICE
A packing method for a semiconductor device includes a step of preparing the semiconductor device that has a sealing body having a principal surface and a...
2018/0005844 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element,...
2018/0005840 Surface Treatment in a Chemical Mechanical Process
A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high...
2018/0005839 ENVIRONMENTALLY GREEN PROCESS AND COMPOSITION FOR COBALT WET ETCH
An environmentally green wet etch process for selective removal of cobalt metal generally includes applying water that is free of added buffers, acids, and/or...
2018/0005836 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes feeding a suppression gas, a source gas, a reactive gas, and a purge gas including an inert gas, into a...
2018/0005835 MEMORY DEVICE
Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate...
2018/0005833 HIGH ASPECT RATIO GATES
Embodiments are directed to a method of forming a feature of a semiconductor device. In one or more embodiments, the feature is a gate, and the method includes...
2018/0005831 Method of Reducing an Impurity Concentration in a Semiconductor Body
A method includes kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface...
2018/0005827 MULTI-DEPOSITION PROCESS FOR HIGH QUALITY GALLIUM NITRIDE DEVICE MANUFACTURING
A group III-nitride (III-N)-based electronic device includes an engineered substrate, a metalorganic chemical vapor deposition (MOCVD) III-N-based epitaxial...
2018/0005826 FORMING A SILICON BASED LAYER IN A TRENCH TO PREVENT CORNER ROUNDING
A method of preventing corner rounding for an alternate channel FINFET formed in trenches and the resulting devices are provided. Embodiments include providing...
2018/0005824 A FIELD EFFECT TRANSISTOR USING TRANSITION METAL DICHALCOGENIDE AND A METHOD FOR FORMING THE SAME
In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoS.sub.2 layer....
2018/0005822 GLASS-BASED ARTICLE WITH ENGINEERED STRESS DISTRIBUTION AND METHOD OF MAKING SAME
Disclosed herein are glass-based articles having a first surface having an edge, wherein a maximum optical retardation of the first surface is at the edge and...
2018/0005821 COMBINED REACTIVE GAS SPECIES FOR HIGH-MOBILITY CHANNEL PASSIVATION
A technique relates to in-situ cleaning of a high-mobility substrate. Alternating pulses of a metal precursor and exposure to a plasma of a gas or gas mixture...
2018/0005820 COMPOSITION AND METHOD FOR FORMING A DIELECTRIC LAYER
A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least...
2018/0005817 APPARATUS AND METHOD FOR TREATING SUBSTRATE
Disclosed are an apparatus and a method for liquid-treating a substrate. The method for liquid-treating a substrate includes a first treatment liquid supplying...
2018/0005814 SELECTIVE ATOMIC LAYER DEPOSITION WITH POST-DOSE TREATMENT
Methods and apparatuses for depositing films in high aspect ratio features and trenches using a post-dose treatment operation during atomic layer deposition...
2018/0005813 Manufacturing method for insulation layer, manufacturing method for array substrate and array substrate
A manufacturing method for insulation layer, a manufacturing method for array substrate and an array substrate are disclosed. Wherein, the manufacturing method...
2018/0005811 DEVICE FOR MANIPULATING CHARGED PARTICLES
The present invention is concerned with a device for charged particle transportation and manipulation. Embodiments provide a capability of combining positively...
2018/0005808 COMPOSITIONS, METHODS, AND KITS FOR QUANTIFYING TARGET ANALYTES IN A SAMPLE
A method of quantifying a target analyte by mass spectrometry includes obtaining a mass spectrometer signal comprising a first calibrator signal, comprising a...
2018/0005806 APPARATUS FOR PHYSICAL VAPOR DEPOSITION REACTIVE PROCESSING OF THIN FILM MATERIALS
An apparatus has a cathode target with a cathode target outer perimeter. An inner magnetic array with an inner magnetic array inner perimeter is at the cathode...
2018/0005805 METHOD FOR OPERATION INSTABILITY DETECTION IN A SURFACE WAVE PLASMA SOURCE
Provided are methods and systems for operation instability detection in a surface wave plasma source. In an embodiment a system for plasma processing may...
2018/0005801 APPARATUS AND METHOD FOR DEPOSITION AND ETCH IN GAP FILL
Provided are apparatuses and methods for performing deposition and etch processes in an integrated tool. An apparatus may include a plasma processing chamber...
2018/0005799 MULTI CHARGED PARTICLE BEAM WRITING APPARATUS AND MULTI CHARGED PARTICLE BEAM WRITING METHOD
In one embodiment, a multi charged particle beam writing apparatus includes a blanking plate including a plurality of blankers, bitmap generation processing...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.