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Patent # Description
2018/0019340 PROGRAMMABLE BULK FINFET ANTIFUSES
An antifuse device includes a gate structure formed on a substrate including first spacers formed in an upper portion and a conductive material formed in a...
2018/0019339 METHOD FOR REDUCING CONTACT RESISTANCE IN SEMICONDUCTOR STRUCTURES
Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a...
2018/0019338 Method and Structure for FinFET Devices
A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and...
2018/0019337 METHOD AND STRUCTURE OF FORMING SELF-ALIGNED RMG GATE FOR VFET
An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and...
2018/0019336 THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor integrated circuit device may include an isolating layer, a buried gate, source and drain regions, a dielectric layer having a high dielectric...
2018/0019335 GRADED AND STEPPED EPITAXY FOR CONSTRUCTING POWER CIRCUITS AND DEVICES
An exemplary doping profile for an epitaxial layer reduces the on-state resistance (R.sub.ON) and off-state capacitance (C.sub.D). A reduction in on-state...
2018/0019334 MULTILAYER PASSIVATION OF THE UPPER FACE OF THE STACK OF SEMICONDUCTOR MATERIALS OF A FIELD-EFFECT TRANSISTOR
A field-effect transistor comprising a stack of semiconductor materials, the upper face of the stack being covered with a passivation layer comprises two...
2018/0019333 COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A compound semiconductor device includes: a carrier transit layer; a carrier supply layer over the carrier transit layer; a source electrode and a drain...
2018/0019332 GUARD RINGS FOR CASCODE GALLIUM NITRIDE DEVICES
Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least...
2018/0019331 SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer and a carrier storage layer over the drift layer; a collector...
2018/0019330 LATERAL BIPOLAR JUNCTION TRANSISTOR WITH CONTROLLED JUNCTION
A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and...
2018/0019329 BIPOLAR TRANSISTOR ON HIGH-RESISTIVITY SUBSTRATE
Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity...
2018/0019328 NANOSCALE ELECTRONIC SPIN FILTER
The present invention is in the field of spintronics, and relates to a highly efficient spin filter device, such as a spin-polarizer or a spin valve, and a...
2018/0019327 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The fin...
2018/0019326 SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR AND A METHOD FOR FABRICATING THE SAME
In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from...
2018/0019325 FINFET DEVICE INCLUDING A STEM REGION OF A FIN ELEMENT
A finFET device having a substrate and a fin disposed on the substrate. The fin includes a passive region, a stem region overlying the passive region, and an...
2018/0019324 SEMICONDUCTOR DEVICE HAVING SILICON-GERMANIUM LAYER ON FIN AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the...
2018/0019323 SILICIDATION OF BOTTOM SOURCE/DRAIN SHEET USING PINCH-OFF SACRIFICIAL SPACER PROCESS
A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first...
2018/0019322 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
In case of performing annealing at a temperature of 1300.degree. C. or higher, it is not possible to sufficiently suppress escape of nitrogen from a GaN layer...
2018/0019321 SEMICONDUCTOR DEVICES HAVING 3D CHANNELS, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING 3D CHANNELS
A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the...
2018/0019320 INP-BASED TRANSISTOR FABRICATION
Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A...
2018/0019319 N-CHANNEL BIPOLAR POWER SEMICONDUCTOR DEVICE WITH P-LAYER IN THE DRIFT VOLUME
A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region...
2018/0019318 METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING P-N DIODE
Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage...
2018/0019317 FABRICATION OF AN ISOLATED DUMMY FIN BETWEEN ACTIVE VERTICAL FINS WITH TIGHT FIN PITCH
A method of forming an arrangement of active and inactive fins on a substrate, including forming at least three vertical fins on the substrate, forming a...
2018/0019316 FABRICATION OF AN ISOLATED DUMMY FIN BETWEEN ACTIVE VERTICAL FINS WITH TIGHT FIN PITCH
A method of forming an arrangement of active and inactive fins on a substrate, including forming at least three vertical fins on the substrate, forming a...
2018/0019315 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an...
2018/0019314 Semiconductor Devices Having Work Function Metal Films and Tuning Materials
A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first...
2018/0019313 COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIGHTS AND METHODS OF MANUFACTURING SAME
Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include...
2018/0019312 THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREFOR, OXIDE BACK PLATE AND DISPLAY APPARATUS
Provided are a thin film transistor, a manufacturing method therefor, an oxide back plate and a display apparatus. The thin film transistor comprises: an oxide...
2018/0019311 COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A compound semiconductor device includes: a carrier transit layer; a carrier supply layer over the carrier transit layer; a source electrode and a drain...
2018/0019310 Power Semiconductor Device Having a Field Electrode
A power semiconductor device includes: a semiconductor body for conducting a load current between first and second load terminals; source and channel regions...
2018/0019309 SEMICONDUCTOR DEVICE BASED ON WIDEBAND GAP SEMICONDUCTOR MATERIALS
Methods, systems, and devices are disclosed for implementing a semiconductor device having a transistor and a diode that are monolithically integrated. In one...
2018/0019308 POWER SEMICONDUCTOR DEVICE
The present invention relates to a power semiconductor device which includes: a first conductivity-type silicon carbide semiconductor layer; a switching device...
2018/0019307 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR BASE,...
A method for manufacturing a silicon carbide semiconductor device comprises: a step for forming a front-surface electrode (30) on a front surface side of a...
2018/0019306 Method of Manufacturing Semiconductor Devices and Semiconductor Device Containing Oxygen-Related Thermal Donors
A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen...
2018/0019305 STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)
A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a...
2018/0019304 Semiconductor Device Including a Super Junction Structure in a SiC Semiconductor Body
An embodiment of a semiconductor device includes a body region of a first conductivity type in a SiC semiconductor body of a second conductivity type. A super...
2018/0019303 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
In an element isolation region defining an element formation region, there is formed an element isolation unit including an element isolation unit and the...
2018/0019302 SEMICONDUCTOR DEVICES WITH DEPLETED HETEROJUNCTION CURRENT BLOCKING REGIONS
A semiconductor device includes an upper and lower mirror. At least one active region for light generation is between the upper and lower mirror. At least one...
2018/0019301 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
A semiconductor device may include an element region and a peripheral voltage withstanding region. The peripheral voltage withstanding region includes inner...
2018/0019300 SEMICONDUCTOR DEVICE
A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode...
2018/0019299 TAPERED METAL NITRIDE STRUCTURE
A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located...
2018/0019298 METHOD FOR FORMING PATTERNED TANTALUM NITRIDE (TaN) RESISTORS ON DIELECTRIC MATERIAL PASSIVATION LAYERS
A structure having: a substrate; a passivation layer disposed over a surface of substrate; an etch stop layer disposed on the passivation layer; resistor...
2018/0019297 METHOD AND STRUCTURE FOR DUAL SHEET RESISTANCE TRIMMABLE THIN FILM RESISTORS AT SAME LEVEL
An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the...
2018/0019296 Passive Chip Device and Method of Making the Same
A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two...
2018/0019295 MAGNETIC INDUCTOR STACKS WITH MULTILAYER ISOLATION LAYERS
A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered...
2018/0019294 Display Panel and Display Device
The present application discloses a display panel and a display device. The display panel comprises a substrate, a power supply line layer and a power supply...
2018/0019293 DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
A display device according to an exemplary embodiment of the present inventive concept includes: a substrate; a thin film transistor provided on a first side...
2018/0019292 ELEMENT SUBSTRATE AND LIGHT-EMITTING DEVICE
A potential of a gate of a driving transistor is fixed, and the driving transistor is operated in a saturation region, so that a current is supplied thereto...
2018/0019291 DISPLAY DEVICE
Provided is a display device including a plurality of pixels at least one of which has a first transistor and a light-emitting element. The first transistor...
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