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Patent # Description
2018/0026658 LDPC DECODER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF
An operation method of a LPC decoder includes: initializing variable nodes of a Tanner graph representing a parity check matrix; performing a check node update...
2018/0026657 HIGH-SPEED SERIAL DATA RECEIVING APPARATUS
Provided is a high-speed serial data receiving apparatus including: a clock converter configured to convert a serial clock into a parallel clock; a data...
2018/0026656 TECHNOLOGIES FOR HEURISTIC HUFFMAN CODE GENERATION
Technologies for heuristic Huffman code generation include a computing device that generates a weighted list of symbols for a data block. The computing device...
2018/0026655 TECHNOLOGIES FOR PERFORMING SPECULATIVE DECOMPRESSION
Technologies for performing speculative decompression include a managed node to decode a variable size code at a present position in compressed data with a...
2018/0026654 TECHNOLOGIES FOR HIGH-PERFORMANCE SINGLE-STREAM LZ77 COMPRESSION
Technologies for high-performance single-stream data compression include a computing device that updates an index data structure based on an input data stream....
2018/0026653 TECHNOLOGIES FOR EFFICIENTLY COMPRESSING DATA WITH RUN DETECTION
Technologies for efficiently compressing data with run detection include a compute device. The compute device is to produce a hash as a function of a symbol at...
2018/0026652 TECHNOLOGIES FOR EFFICIENTLY COMPRESSING DATA WITH MULTIPLE HASH TABLES
Technologies for compressing data with multiple hash tables include a compute device. The compute device is to produce, for each of multiple string prefixes of...
2018/0026651 TECHNOLOGIES FOR PERFORMING LOW-LATENCY DECOMPRESSION WITH TREE CACHING
Technologies for performing low-latency decompression include a managed node to parse, in response to a determination that a read tree descriptor does not...
2018/0026650 ENCODING DEVICE, ENCODING METHOD AND SEARCH METHOD
A recording medium having stored therein an encoding program that causes a computer to execute a process, the process including first generating a plurality of...
2018/0026649 METHOD FOR DATA COMPRESSION
A data compression system includes: (a) a data compression module that receives a sequence of input vectors and that provides a sequence of compressed vectors;...
2018/0026648 Time-Based Delay Line Analog Comparator
Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog...
2018/0026647 COMPARATOR, CIRCUIT DEVICE, PHYSICAL QUANTITY SENSOR, ELECTRONIC DEVICE, AND VEHICLE
A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit...
2018/0026646 MULTIPLE-OUTPUT OSCILLATOR CIRCUITS
A phase-locked loop (PLL) circuit may be configured to generate a plurality of oscillating signals based on a single control voltage generated based on a phase...
2018/0026645 Magnetoelectric Computational Devices
Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational...
2018/0026644 COMPENSATION MEMORY (CM) FOR POWER APPLICATION
A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data....
2018/0026643 NOISE-IMMUNIE REFERENCE (NREF) INTERGARED IN A PROGRAMMABLE LOGIC DEVICE
A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive...
2018/0026642 FEEDBACK CONTROL SYSTEMS WITH PULSE DENSITY SIGNAL PROCESSING CAPABILITIES
A feedback control system may include a feedback controller for controlling a plant using pulse density signals. The feedback controller may include a pulse...
2018/0026641 FPGA RAM Blocks Optimized for Use as Register Files
A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array...
2018/0026640 SCALABLE INTEGRATED MOSFET (SIM)
A high voltage power block includes a high voltage power transistor; and a switch driver configured to drive a gate of the high voltage power transistor. The...
2018/0026639 A SEMICONDUCTOR LOGIC ELEMENT AND A LOGIC CIRCUITRY
Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second...
2018/0026638 Apparatus For Configurable Interface And Associated Methods
An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened...
2018/0026637 PRECISION MODULATION TIMER (PMT) INTEGRATED IN A PROGRAMMALBE LOGIC DEVICE
A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital...
2018/0026636 PROGRAMMABLE ANALOG AND DIGITAL INPUT/OUTPUT FOR POWER APPLICATION
A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal...
2018/0026635 VOLTAGE LEVEL TRANSLATION CIRCUIT AND MULTIPLE INTERFACE IN COMMUNICATION SYSTEM
A voltage level translation circuit includes a first energy storage unit, a second energy storage unit, a first voltage level translation unit, and a second...
2018/0026634 ON-DIE TERMINATION CIRCUIT, A MEMORY DEVICE INCLUDING THE ON-DIE TERMINATION CIRCUIT, AND A MEMORY SYSTEM...
An on-die termination (ODT) circuit connected to an input buffer that receives a data signal, the ODT circuit includes at least one termination resistor...
2018/0026633 SUPERCONDUCTING SINGLE-POLE DOUBLE-THROW SWITCH SYSTEM
A superconducting switch system is provided that includes a filter network having a first SQUID coupled to a second SQUID via a common node, an input port...
2018/0026632 ULTRA-LOW POWER CROSS-POINT ELECTRONIC SWITCH APPARATUS AND METHOD
An electrical switch circuit adapted to switch digital, high-speed signals with low power includes a plurality of input buffers each coupled to an input...
2018/0026631 BIASING SCHEME FOR HIGH VOLTAGE CIRCUITS USING LOW VOLTAGE DEVICES
Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to...
2018/0026630 CIRCUIT WITH TRANSISTORS HAVING COUPLED GATES
A circuit can include a first transistor including a source and a gate; a second transistor including a drain and a gate, wherein the source of the first...
2018/0026629 OUTPUT DRIVER HAVING PULL-DOWN CAPABILITY
An output driver includes a switching device having a first node coupled to a gate of a power switch and pulling down a voltage level of the gate of the power...
2018/0026628 HYBRID SWITCH INCLUDING GAN HEMT AND MOSFET
A hybrid switch apparatus includes a gate drive circuit producing a gate drive signal, a GaN high electron mobility transistor (HEMT) having a first gate, a...
2018/0026627 LEVEL SHIFTER
A level shifter includes a driving circuit, which receives an input signal and outputs a driving signal in response to a first voltage level of the input...
2018/0026626 ADAPTIVE GATE DRIVER
A device driver is described that includes an output stage and one or more control components. The output stage is configured to produce a gate driver output...
2018/0026625 PROGRAMMABLE CURRENT FOR CORRELATED ELECTRON SWITCH
Subject matter disclosed herein may relate to programmable current for correlated electron switches.
2018/0026624 HALF-BRIDGE DRIVER FAULT DIAGNOSTIC SYSTEM AND METHOD
An apparatus for controlling the application of electrical power to a load includes a controller, a controllable high side driver electrically connected to a...
2018/0026623 SOLID STATE SWITCH SYSTEM
A solid state switch for connecting and disconnecting an electrical device has at least one FET-type device and at least one thyristor-type device coupled in...
2018/0026622 APPARATUSES AND METHODS FOR REDUCING OFF STATE LEAKAGE CURRENTS
Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having...
2018/0026621 CORRELATED ELECTRON SWITCH
Subject matter disclosed herein may relate to correlated electron switches.
2018/0026620 OVERVOLTAGE PROTECTION CIRCUIT
Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground....
2018/0026619 POWER SOURCE SUPPLY CIRCUIT, AMPLIFIER, COMMUNICATION DEVICE, BASE STATION, AND POWER SOURCE SUPPLY METHOD
A power source supply circuit includes: a plurality of power sources (11-1, 11-2) that generate power source voltages different from each other; a switch...
2018/0026618 HIGH-SPEED CONTINUOUS-TIME COMPARATOR CIRCUIT
A comparator circuit including: a first node and a second node, which receive a first current and a second current, respectively; a first current mirror, which...
2018/0026617 CIRCUIT DEVICE, ELECTRONIC DEVICE, PHYSICAL QUANTITY SENSOR, AND VEHICLE
A circuit device includes a comparator and a flag signal generation circuit. The comparator includes a first voltage-time conversion circuit to which at least...
2018/0026616 INPUT DEVICE
The embodiment relates to an input device comprises first and second MOS transistors, first to fourth resistors, and a comparator circuit. The first MOS...
2018/0026615 COMPARATOR, CIRCUIT DEVICE, PHYSICAL QUANTITY SENSOR, ELECTRONIC DEVICE, AND VEHICLE
A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit...
2018/0026614 SEMICONDUCTOR DEVICE
A semiconductor device includes an input determination circuit. The input determination circuit includes: a comparator that is driven based on a first...
2018/0026613 BALANCING DELAY ASSOCIATED WITH DUAL-EDGE TRIGGER CLOCK GATERS
Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock...
2018/0026612 SEMICONDUCTOR DEVICE
To provide an asynchronous circuit capable of power gating, a semiconductor device is configured with first to third terminals, a latch circuit, and a memory...
2018/0026611 SIGNAL TRANSMISSION CIRCUIT AND VEHICLE
A signal transmission circuit which transmits N (N is a natural number of 2 or more) input signals includes a transmission signal generation portion, 2.sup.N...
2018/0026610 LATCH CIRCUITRY
Circuitry is configured to store data in response to a phase transition of an input clock. The circuitry uses a master-slave latch configuration. Each of the...
2018/0026609 METHOD FOR COMPENSATING EFFECTS OF SUBSTRATE STRESSES IN SEMICONDUCTOR DEVICES, AND CORRESPONDING DEVICE
A semiconductor substrate includes a first portion and a second portion. The first portion of the substrate has a first deformation-stress sensor capable of...
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