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Patent # Description
2018/0026051 DISPLAY SUBSTRATE, METHOD FOR PRODUCING THE SAME, AND DISPLAY APPARATUS
Embodiments of this invention relate to a display substrate and a method for producing the same, as well as a display apparatus. The display substrate...
2018/0026050 Semiconductor Devices with Vertical Channel Structures
Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel...
2018/0026049 SEMICONDUCTOR MEMORY DEVICES HAVING VERTICAL PILLARS THAT ARE ELECTRICALLY CONNECTED TO LOWER CONTACTS
A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the...
2018/0026048 NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME
According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor...
2018/0026047 MEMORY DEVICE
A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a...
2018/0026046 MEMORY DEVICE
In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At...
2018/0026045 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device according to an embodiment comprises a substrate, a plurality of first conductive films, a memory columnar body, and a first...
2018/0026044 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a plurality of word lines stacked in a first direction; a semiconductor pillar extending through the plurality of word...
2018/0026043 VERTICALLY STACKED FINFET FUSE
A semiconductor structure including a stacked FinFET fuse is provided in which the stacked FinFET fuse includes a plurality of vertically stacked and spaced...
2018/0026042 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the...
2018/0026041 Vertical Memory Devices and Methods of Manufacturing the Same
Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region,...
2018/0026040 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes stacking a molding layer and a preliminary support layer on a substrate, forming a support layer...
2018/0026039 SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD THEREOF
A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate...
2018/0026038 FETS and Methods of Forming FETS
A method includes forming a first semiconductor strip on a substrate, the first semiconductor strip including a first crystalline semiconductor material on a...
2018/0026037 Display Device and Electronic Device
A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The...
2018/0026036 INTEGRATED CIRCUIT COMPRISING TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES
An integrated circuit comprising: first to third nMOS transistors with different threshold voltages, and first to third pMOS transistors with different...
2018/0026035 STRUCTURE AND METHOD TO SUPPRESS WORK FUNCTION EFFECT BY PATTERNING BOUNDARY PROXIMITY IN REPLACEMENT METAL GATE
A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second...
2018/0026034 SEMICONDUCTOR STRUCTURE WITH LOW DEFECT
Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and an isolation structure formed around...
2018/0026033 METHODS FOR FABRICATING FIN FIELD EFFECT TRANSISTORS
Method for fabricating Fin field effect transistors (FinFETs) are disclosed. One of the methods includes the following steps. A first semiconductor fin, a...
2018/0026032 SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a...
2018/0026031 Semiconductor Structure with Resistor Layer and Method for Forming the Same
A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate...
2018/0026030 PROTECTION CIRCUIT AND PROTECTION CIRCUIT SYSTEM
The present technique relates to a protection circuit for a MOSFET and a protection circuit system including the protection circuit all of which can reduce...
2018/0026029 Integrated ESD Protection Circuit for GaN Based Device
The present disclosure relates to an electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured...
2018/0026028 METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING TRIGGER-VOLTAGE TUNABLE CASCODE TRANSISTORS
Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include...
2018/0026027 OVERVOLTAGE PROTECTION DEVICE
An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity...
2018/0026026 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE RELATING TO AN ELECTRICAL OVER STRESS PROTECTING CIRCUIT
A semiconductor integrated circuit device may include a first discharging unit and a second discharging unit. The first discharging unit may be coupled between...
2018/0026025 TVS STRUCTURES FOR HIGH SURGE AND LOW CAPACITANCE
A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device...
2018/0026024 SEMICONDUCTOR DEVICE
An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second...
2018/0026023 Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is...
2018/0026022 SOLID STATE DRIVE PACKAGE
A solid state drive package is provided. The solid state drive package may include an integrated circuit substrate including: a lower redistribution layer; a...
2018/0026021 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first element formed of a first constituent as a main constituent; a second element formed of a second constituent as a main...
2018/0026020 COMPACT OPTOELECTRONIC MODULES
Compact optoelectronic modules are described that, in some implementations, can have reduced heights, while at the same time having very little optical...
2018/0026019 Package-on-Package Devices with WLP Components with Dual RDLS for Surface Mount Dies and Methods Therefor
Package-on-package ("PoP") devices with WLP ("WLP") components with dual RDLs ("RDLs") for surface mount dies and methods therefor. In a PoP, a first IC die...
2018/0026018 Package-on-Package Devices with Multiple Levels and Methods Therefor
Package-on-package ("PoP") devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount...
2018/0026017 Dies-on-Package Devices and Methods Therefor
Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a...
2018/0026016 Package-on-Package Devices with Upper RDL of WLPS and Methods Therefor
Package-on-package ("PoP") devices with upper RDLs of WLP ("WLP") components and methods therefor are disclosed. In a PoP device, a first IC die is surface...
2018/0026015 INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS
Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die...
2018/0026014 Package-on-Package Structure with Through Molding Via
Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the...
2018/0026013 MEMORY DEVICE INCLUDING INTERPOSER AND SYSTEM-IN-PACKAGE INCLUDING THE SAME
A memory device including an interposer including a first plurality of paths and a second plurality of paths, a first memory die attached to a first surface of...
2018/0026012 MULTILAYER SUBSTRATE
Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent...
2018/0026011 Package-on-Package Devices with Same Level WLP Components and Methods Therefor
Package-on-package ("PoP") devices with same level wafer-level packaged ("WLP") components and methods therefor are disclosed. In a PoP device, a first...
2018/0026010 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second...
2018/0026009 POWER MODULE, ELECTRICAL POWER CONVERSION DEVICE, AND DRIVING DEVICE FOR VEHICLE
The object of the present invention is to compensate for a difference in threshold voltage between a plurality of switching devices incorporated in a power...
2018/0026008 3D Semiconductor Package Interposer with Die Cavity
Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or...
2018/0026007 PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements...
2018/0026006 SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS
A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first...
2018/0026004 BONDING WIRE, WIRE BONDING METHOD USING THE BONDING WIRE, AND ELECTRICAL CONNECTION PART OF SEMICONDUCTOR...
A bonding wire includes a wire core including a silver-palladium alloy, and a coating layer disposed on a sidewall of the wire core. A palladium content of the...
2018/0026003 ELECTRICALLY CONDUCTIVE ADHESIVE FILM AND DICING DIE BONDING FILM
A means that exhibits excellent heat resistance and mounting reliability when bonding a power semiconductor device on to a metal lead frame, which is also...
2018/0026002 Under Bump Metallurgy (UBM) And Methods Of Forming Same
A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises...
2018/0026001 Integrated Fan-Out Structure and Method of Forming
Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer...
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