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Patent # Description
2018/0026000 Integrated Passive Device for RF Power Amplifier Package
The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising...
2018/0025999 INFO PACKAGE WITH INTEGRATED ANTENNAS OR INDUCTORS
In some embodiments, a semiconductor package includes a die surrounded by a molding material, a redistribution layer over the die and the molding material, the...
2018/0025998 SEMICONDUCTOR DEVICE
A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a...
2018/0025997 SEMICONDCUTOR STRUCTURE AND SEMICONDUCTOR MANUFACTURING PROCESS THEREOF
A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold...
2018/0025996 PROTECTED INTEGRATED CIRCUIT
The integrated circuit includes a functional block performing a logic and/or analog function. A control circuit is configured to transmit at least a first...
2018/0025995 REDUCING WAFER WARPAGE DURING WAFER PROCESSING
According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a first guard ring around a first...
2018/0025994 SURFACE MOUNT PACKAGE AND MANUFACTURING METHOD THEREOF
An object of the present invention is to provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress....
2018/0025993 SEMICONDUCTOR DEVICE
According to the present invention, a semiconductor device includes a heat spreader, a semiconductor chip fixed to a mounting surface of the heat spreader via...
2018/0025992 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution...
2018/0025991 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment...
2018/0025990 PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT
A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion...
2018/0025989 FORMATION OF LINER AND METAL CONDUCTOR
An integrated circuit device includes a substrate including a dielectric layer patterned with a set of conductive line trenches, each conductive line trench...
2018/0025988 SIMULTANEOUS FORMATION OF LINER AND METAL CONDUCTOR
An advanced metal conductor structure and a method for constructing the structure are described. A method for fabricating an advanced metal conductor structure...
2018/0025987 Wafer-Level Packaged Components and Methods Therefor
Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of...
2018/0025986 INTEGRATED FAN-OUT PACKAGE
A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one...
2018/0025985 FAN-OUT PACKAGE STRUCTURE
A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided....
2018/0025984 SEMICONDUCTOR DEVICE HAVING STRUCTURE FOR IMPROVING VOLTAGE DROP AND DEVICE INCLUDING THE SAME
A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers...
2018/0025983 DESIGNABLE CHANNEL FINFET FUSE
On-chip, doped semiconductor fuse regions compatible with FinFET CMOS fabrication are formed from the channel regions of selected fins. One or more fin...
2018/0025982 SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL ONE-TIME-PROGRAMMABLE FUSE
A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating...
2018/0025981 METHOD FOR PROVIDING ELECTRICAL ANTIFUSE INCLUDING PHASE CHANGE MATERIAL
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further...
2018/0025980 ELECTRICAL ANTIFUSE HAVING AIRGAP OR SOLID CORE
An antifuse structure including an opening through a dielectric material to a contact surface and an antifuse material layer present within the opening. The...
2018/0025979 ELECTRICAL ANTIFUSE
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further...
2018/0025978 METHOD OF MAKING ELECTRICAL ANTIFUSE
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further...
2018/0025977 ELECTRICAL ANTIFUSE HAVING AIRGAP OR SOLID CORE
An antifuse structure including an opening through a dielectric material to a contact surface and an antifuse material layer present within the opening. The...
2018/0025976 METHOD FOR PROVIDING ELECTRICAL ANTIFUSE INCLUDING PHASE CHANGE MATERIAL
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further...
2018/0025975 INTERCONNECTION STRUCTURE AND METHOD OF FORMING THE SAME
An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure and a conductive structure. The liner layer is present...
2018/0025974 INTEGRATING METAL-INSULATOR-METAL CAPACITORS WITH AIR GAP PROCESS FLOW
Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect...
2018/0025973 CHIP
The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging...
2018/0025972 POWER LINE LAYOUT STRUCTURE FOR SEMICONDUCTOR DEVICE
A power line layout structure of the semiconductor device may include first through fifth power lines. The first and second power lines may be located at a...
2018/0025971 SIMULTANEOUS FORMATION OF LINER AND METAL CONDUCTOR
An integrated circuit device having a substrate including a dielectric layer is patterned with a set of conductive line trenches. Each conductive line trench...
2018/0025970 INTEGRATED CIRCUIT (IC) STRUCTURE FOR HIGH PERFORMANCE AND FUNCTIONAL DENSITY
An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL...
2018/0025969 METAL CAP INTEGRATION BY LOCAL ALLOYING
A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal...
2018/0025968 SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT
The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate...
2018/0025967 FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES
A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The...
2018/0025966 INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME
Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of...
2018/0025965 WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method Therefor
A quad flat no lead package is provided comprising at least one first integrated circuit die embedded in a recess in a die paddle of a metal leadframe and a...
2018/0025964 FLUID-FILLED MICROCHANNELS
A device comprises a first layer of a die. The first layer comprises a microchannel. The microchannel is partially filled with a liquid and partially filled...
2018/0025963 METHOD, SYSTEM, AND ELECTRONIC ASSEMBLY FOR THERMAL MANAGEMENT
There are provided methods, systems, and electronic assemblies for efficient thermal management in electronics applications. For example, there is provided an...
2018/0025962 Power Electronics Assemblies Having a Semiconductor Device with Metallized Embedded Cooling Channels
A power electronics assembly having a semiconductor device that includes a first device surface opposite a second device surface, a semiconductor substrate...
2018/0025961 Power Conversion Device Including Semiconductor Module Provided with Laminated Structure
A power conversion device includes a semiconductor module with switching elements incorporated therein, a plurality of components electrically connected to the...
2018/0025960 CIRCUIT PACKAGE
A circuit package panel containing a packaging of epoxy mold compounds and a circuit device in the packaging, wherein the packaging comprises, at least one...
2018/0025959 Integrated Circuit Packages and Methods for Forming the Same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector...
2018/0025958 BASE-ATTACHED ENCAPSULANT FOR SEMICONDUCTOR ENCAPSULATION, SEMICONDUCTOR APPARATUS, AND METHOD FOR...
A base-attached encapsulant for semiconductor encapsulation is used for collectively encapsulating a device-mounted surface of the semiconductor device-mounted...
2018/0025957 POLYPHENYLENE SULFIDE RESIN COMPOSITION, MOLDED PRODUCT FORMED THEREFROM AND METHOD OF PRODUCING SEMICONDUCTOR...
A polyphenylene sulfide resin composition includes 5-50% by weight of (A) a polyphenylene sulfide resin having a weight-average molecular weight of not less...
2018/0025956 MANUFACTURING METHOD OF PACKAGE CARRIER
A manufacturing method of a package carrier is provided. A substrate having a through hole is provided, wherein a profile of the through hole from top view is...
2018/0025955 SEMICONDUCTOR DEVICE AND METHOD
Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer....
2018/0025954 TOP CONTACT RESISTANCE MEASUREMENT IN VERTICAL FETS
A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode...
2018/0025953 INSPECTING METHOD FOR INSPECTING INFLUENCE OF INSTALLATION ENVIRONMENT UPON PROCESSING APPARATUS
A method for inspecting the influence of an installation environment upon a processing apparatus includes setting a mark for specifying a relative positional...
2018/0025952 Reverse Decoration for Defect Detection Amplification
Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void,...
2018/0025951 INFORMATION PROCESSING DEVICE, PROCESSING DEVICE, PREDICTION METHOD, PROGRAM, AND PROCESSING METHOD
Efficiency of prediction of a physical quantity increases in repeated simulation of an etching process with a change of parameters. An information processing...
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