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Patent # Description
2018/0025950 TOP CONTACT RESISTANCE MEASUREMENT IN VERTICAL FETS
A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode...
2018/0025949 METHOD OF MEASURING MISALIGNMENT OF CHIPS, A METHOD OF FABRICATING A FAN-OUT PANEL LEVEL PACKAGE USING THE...
A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated...
2018/0025948 METHOD OF MANUFACTURING A CMOS TRANSISTOR
A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the...
2018/0025947 METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE
A method of manufacturing an integrated circuit device includes providing a substrate with a pattern structure, the pattern structure including a plurality of...
2018/0025946 FINFET Channel on Oxide Structures and Related Methods
A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate....
2018/0025945 PNP-TYPE BIPOLAR TRANSISTOR MANUFACTURING METHOD
A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type...
2018/0025944 SELF-ALIGNED CONTACT CAP
A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first...
2018/0025943 ALIGNING CONDUCTIVE VIAS WITH TRENCHES
A method for forming conductive contacts on a wafer comprises forming a first hardmask, planarizing layer, second hardmask, and a layer of sacrificial mandrel...
2018/0025942 SELF-ALIGNED CONTACT CAP
A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first...
2018/0025941 INTERCONNECT STRUCTURE AND FABRICATION THEREOF
Interconnect structures and processes generally include creating point defects in exposed surfaces of the dielectric layer to create a point defect region at a...
2018/0025940 METHOD FOR REMOVING BARRIER LAYER FOR MINIMIZING SIDEWALL RECESS
Provided is a method for removing barrier layer for minimizing sidewall recess. The method comprises the following steps: introduce noble-gas-halogen compound...
2018/0025939 SELECTIVE DEPOSITION OF TUNGSTEN
A method for selectively depositing a metal film onto a substrate is disclosed. In particular, the method comprising flowing a metal precursor onto the...
2018/0025938 Method of Forming Trenches with Different Depths
A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the...
2018/0025937 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device may include forming an insulating layers on a substrate, forming a plurality of holes in an upper portion of...
2018/0025936 LITHOGRAPHIC PATTERNING TO FORM FINE PITCH FEATURES
Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed...
2018/0025935 SEMICONDUCTOR STRUCTURE HAVING AN ISOLATION LAYER FOR REDUCING PARASITIC EFFECT
A semiconductor structure includes a first well, a semiconductor element, a second well and a first isolation layer. The semiconductor element is formed on or...
2018/0025934 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
A semiconductor integrated circuit device may include a first electrostatic discharge (ESD) protecting circuit and a second ESD protecting circuit. The first...
2018/0025933 ELECTROSTATIC CHUCK DEVICE, AND SEMICONDUCTOR MANUFACTURING DEVICE
An electrostatic chuck part of an electrostatic chuck device has an electrostatic chuck part inner peripheral surface surrounding an opening of a chuck part...
2018/0025932 LAMINATED TOP PLATE OF A WORKPIECE CARRIER IN MICROMECHANICAL AND SEMICONDUCTOR PROCESSING
A laminated top plate of a workpiece carrier is described that is particularly suitable for mechanical and semiconductor processing. In one example, A method...
2018/0025931 PROCESSED WAFER AS TOP PLATE OF A WORKPIECE CARRIER IN SEMICONDUCTOR AND MECHANICAL PROCESSING
A processed wafer is described that may be used as a workpiece carrier in semiconductor and mechanical processing. In some examples, the workpiece carrier...
2018/0025930 CONTROL OF WAFER BOW IN MULTIPLE STATIONS
A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and...
2018/0025929 SYSTEMS AND METHODS FOR SENSING PROCESS PARAMETERS DURING SEMICONDUCTOR DEVICE FABRICATION
Semiconductor device fabrication systems and methods are provided. In an example, a semiconductor device fabrication system includes a semiconductor...
2018/0025928 HOLD CHECKING METHOD AND UNHOLD CHECKING METHOD FOR WAFER
Disclosed herein is a hold checking method for checking whether or not a wafer is held by an electrostatic chuck in loading the wafer to the electrostatic...
2018/0025927 SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD, AND STORAGE MEDIUM
The substrate liquid processing apparatus includes a processing bath that accommodates substrates, and a plurality of gas supply pipes provided in a processing...
2018/0025926 SUBSTRATE PROCESSING APPARATUS
A substrate processing apparatus includes an outer tube including an open bottom portion and a closed top portion, and an inner tube disposed in the outer tube...
2018/0025925 WAFER HOLDER AND TEMPERATURE CONDITIONING ARRANGEMENT AND METHOD OF MANUFACTURING A WAFER
A wafer holder and temperature controlling arrangement has a metal circular wafer carrier plate, which covers a heater compartment. In the heater compartment a...
2018/0025924 METHODS AND APPARATUS FOR RAPIDLY COOLING A SUBSTRATE
Methods and apparatus for changing the temperature of a substrate are provided. In some embodiments, a method includes: placing a substrate onto a support...
2018/0025923 PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD
A plasma processing apparatus includes: a processing container which defines a processing space; a microwave generator; a dielectric having an opposing surface...
2018/0025921 SUBSTRATE TREATING APPARATUS
Disclosed is a substrate treating apparatus that treats a substrate with processing liquids. The apparatus includes a substrate holder, an exterior cup, and an...
2018/0025920 SUBSTRATE PROCESSING APPARATUS
A substrate processing apparatus includes: a plurality of modules configured to process a substrate; a transfer chamber adjoining the modules; a transfer part...
2018/0025919 METHOD FOR PRODUCING SILICON CARBIDE COMPOSITE MATERIAL
A silicon carbide composite that is lightweight and has high thermal conductivity as well as a low thermal expansion coefficient close to that of a ceramic...
2018/0025918 METHOD FOR MANUFACTURING TRANSISTOR AND DISPLAY DEVICE
A transistor with high productivity and a method for manufacturing the transistor are provided. In the formation of a bottom-gate transistor using a metal...
2018/0025917 METHOD OF FABRICATING SEMICONDUCTOR DEVICE, VACUUM PROCESSING APPARATUS AND SUBSTRATE PROCESSING APPARATUS
There is provided a method of fabricating a semiconductor device by performing a process on a substrate, which includes: forming a masking film made of a...
2018/0025916 MONOLAYER FILM MEDIATED PRECISION MATERIAL ETCH
A method of etching is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to...
2018/0025915 DRY ETCHING METHOD
A dry etching method includes performing at least two etching steps, and further includes injecting protective gas into an etch chamber for processing between...
2018/0025914 METHODS FOR HIGH TEMPERATURE ETCHING A MATERIAL LAYER USING PROTECTION COATING
Methods for etching a bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) to form...
2018/0025913 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device with favorable electrical characteristics is provided. A source electrode and a drain electrode of a channel-etched transistor are each...
2018/0025912 P-TYPE IMPURITY-DIFFUSING COMPOSITION, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAID COMPOSITION,...
A p-type impurity diffusion composition is provided which makes it possible to improve storage stability of a coating liquid, and to achieve uniform diffusion...
2018/0025911 Monolithic Integration of Semiconductor Materials
A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a...
2018/0025910 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE,...
A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC...
2018/0025909 THIN FILM, METHOD OF FABRICATING THE SAME, AND APPARATUS FOR FABRICATING THE SAME
An apparatus for fabricating a thin film is provided. The apparatus includes a tube including one end and another end, a first heater supplying heat to a first...
2018/0025908 MONOLAYER FILM MEDIATED PRECISION FILM DEPOSITION
A method of forming a thin film is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting...
2018/0025907 Deposition Of Flowable Silicon-Containing Films
Methods for seam-less gapfill comprising forming a flowable film by exposing a substrate surface to a silicon-containing precursor and a co-reactant are...
2018/0025906 SILICON CHALCOGENATE PRECURSORS, METHODS OF FORMING THE SILICON CHALCOGENATE PRECURSORS, AND RELATED METHODS OF...
A silicon chalcogenate precursor comprising the chemical formula of Si(XR.sup.1).sub.nR.sup.2.sub.4-n, where X is sulfur, selenium, or tellurium, R.sup.1 is...
2018/0025905 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device having favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device...
2018/0025904 Systems and Methods for Treating Substrates with Cryogenic Fluid Mixtures
Disclosed herein are systems and methods for treating the surface of a microelectronic substrate, and in particular, relate to an apparatus and method for...
2018/0025903 TOOLS & METHODS FOR PRODUCING NANOANTENNA ELECTRONIC DEVICES
The present disclosure advances the art by providing a method and system for forming electronic devices. In particular, and by example only, methods are...
2018/0025902 High Throughput Semiconductor Deposition System
A reactor for growing or depositing semiconductor films or devices. The reactor may be designed for inline production of III-V materials grown by hydride vapor...
2018/0025901 Precleaning Apparatus and Substrate Processing System
A precleaning apparatus includes a chamber having an internal space in which a substrate is cleaned, a substrate support disposed in the chamber and configured...
2018/0025900 ALKALI METAL AND ALKALI EARTH METAL REDUCTION
Methods of removing contamination from the surface of a substrate are described. The etch selectively removes alkali metals and alkali earth metals from...
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