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Patent # Description
2018/0033826 VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer...
2018/0033825 THERMAL MANAGEMENT OF SELECTOR
A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory...
2018/0033824 LIGHT-EMITTING STRUCTURE
A light-emitting structure includes an epitaxial structure including a plurality of trenches; a conductive connecting layer, disposed under the epitaxial...
2018/0033822 HIGH-PERFORMANCE RADIATION DETECTORS AND METHODS OF FABRICATING THEREOF
A method of fabricating a solid state radiation detector method includes mechanically lapping and polishing the first and the second surfaces of a ...
2018/0033821 ORGANIC LIGHT EMITTING DISPLAY DEVICE
An organic light emitting display device includes a substrate in which an active area and a bending area are defined, a thin film transistor on the substrate...
2018/0033820 Semiconductor Image Sensor Device Having Back Side Illuminated Image Sensors with Embedded Color Filters
Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region,...
2018/0033819 TERAHERTZ CMOS SENSOR
An imaging sensor for accepting terahertz signals, including a die made of a dielectric material, one or more antennas for receiving terahertz signals,...
2018/0033818 Time-Of-Flight Image Sensor and Light Source Driver Having Simulated Distance Capability
An apparatus is described that includes an image sensor and a light source driver circuit having configuration register space to receive information pertaining...
2018/0033817 3DIC Seal Ring Structure and Methods of Forming Same
A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive...
2018/0033816 IMAGING ELEMENT, IMAGING DEVICE, AND MANUFACTURING APPARATUS AND METHOD
The present technology relates to an imaging element, an imaging device, and a manufacturing apparatus and a method that facilitate electric charge transfer....
2018/0033815 Photo Sensor
Some embodiments described herein are directed to a photo sensor and a method of operating a photo sensor. In an embodiment, a photo sensor comprises a photo...
2018/0033814 Photo Sensor
Some embodiments described herein are directed to a photo sensor and a method of operating a photo sensor. In an embodiment, a photo sensor comprises a photo...
2018/0033813 SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE PICKUP ELEMENT, IMAGING DEVICE, AND ELECTRONIC APPARATUS
The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress...
2018/0033812 MECHANISMS FOR FORMING IMAGE-SENSOR DEVICE WITH EXPITAXIAL ISOLATION FEATURE
An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded...
2018/0033811 BIASED DEEP TRENCH ISOLATION
An image sensor includes a plurality of photodiodes disposed in a semiconductor material, and a through-semiconductor-via coupled to a negative voltage source....
2018/0033810 METHOD FOR FORMING SHALLOW TRENCHES OF THE DUAL ACTIVE REGIONS
The invention disclosed a method for forming shallow trenches of the dual active regions. Firstly, forming an etch stop layer on a semiconductor substrate;...
2018/0033809 SOLID-STATE IMAGE SENSING DEVICE AND ELECTRONIC DEVICE
The present technology relates to a solid-state image sensing device and an electronic device capable of reducing noises. The solid-state image sensing device...
2018/0033808 MANUFACTURING METHOD FOR LTPS TFT SUBSTRATE
The invention provides a manufacturing method for LTPS TFT substrate. After forming N+ areas on both sides of polysilicon layer, the first gate insulating...
2018/0033807 TRANSISTOR, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate...
2018/0033806 ARRAY SUBSTRATE AND DISPLAY PANEL
The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of signal lines, a plurality of secondary...
2018/0033805 Displays With Silicon and Semiconducting Oxide Thin-Film Transistors
An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display...
2018/0033804 Thin Film Transistor, Method for Manufacturing the Same, and Display Device Including the Same
Disclosed is a thin film transistor including both an N-type semiconductor layer and a P-type semiconductor layer, a method for manufacturing the same, and a...
2018/0033803 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A display substrate includes a base substrate, a switching element disposed on the base substrate a first layer disposed on the switching element, a first...
2018/0033802 ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, DISPLAY PANEL, AND DISPLAY DEVICE
An array substrate, a manufacturing method thereof, a display panel and a display device are disclosed. The manufacturing method includes: forming a first...
2018/0033801 DISPLAY DEVICE
According to one embodiment, a display device includes a first substrate including a first basement, a scanning line extending along the first direction, a...
2018/0033800 DISPLAY DEVICE
According to one embodiment, a display device includes a first substrate including a first basement, a scanning line and a signal line, arranged in a display...
2018/0033799 VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack...
2018/0033798 NON-VOLATILE MEMORY WITH REDUCED VARIATIONS IN GATE RESISTANCE
A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over...
2018/0033797 NON-VOLATILE MEMORY DEVICE HAVING NANOCRYSTAL FLOATING GATE AND METHOD OF FABRICATING SAME
Methods are disclosed herein for fabricating non-volatile memory devices. An exemplary method forms a heterostructure over a substrate. The heterostructure...
2018/0033796 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed...
2018/0033795 One-Time Programmable Bitcell with Native Anti-Fuse
An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping...
2018/0033794 Non-Volatile Memory With Reduced Program Speed Variation
A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top...
2018/0033793 Thin SRAM Cell Having Vertical Transistors
A memory device includes six field effect transistors (FETs) formed with semiconductor nanowires arranged on a substrate in an orientation substantially...
2018/0033792 PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR PRODUCING THE SAME
An SRAM includes two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each...
2018/0033791 DRAM CELL FOR REDUCING LAYOUT AREA AND FABRICATING METHOD THEREOF
The fabricating method of a DRAM cell includes forming a facing bar that extends in a direction of the word line; forming a gate of the cell transistor on one...
2018/0033790 INCREASING THICKNESS OF FUNCTIONAL LAYER ACCORDING TO INCREASING RECESS AREA
A method of manufacturing a semiconductor device includes providing a substrate having first and second semiconductor fins, forming an insulating layer on the...
2018/0033789 METHOD, APPARATUS, AND SYSTEM FOR REDUCING DOPANT CONCENTRATIONS IN CHANNEL REGIONS OF FINFET DEVICES
We disclose semiconductor devices, comprising a semiconductor substrate comprising a substrate material; and a plurality of fins disposed on the substrate,...
2018/0033788 VERTICAL FIELD EFFECT TRANSISTOR WITH UNIFORM GATE LENGTH
Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a...
2018/0033787 METHODS OF FABRICATING INTEGRATED CIRCUITS AND DEVICES WITH INTERLEAVED TRANSISTOR ELEMENTS
A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in...
2018/0033786 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
2018/0033785 SEMICONDUCTOR DEVICE
A semiconductor device includes a first overvoltage detection unit including a first comparator arranged to output a first detection signal based on a first...
2018/0033784 VARIABLE HOLDING VOLTAGE SILICON CONTROLLED RECTIFIER USING SEPARATE AND DISTINCT BIPOLARS
A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of...
2018/0033783 Avalanche Diode Having an Enhanced Defect Concentration Level and Method of Making the Same
The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the...
2018/0033782 USING METAL-CONTAINING LAYER TO REDUCE CARRIER SHOCK IN PACKAGE FORMATION
A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation...
2018/0033781 METHODS OF MANUFACTURING MULTI-DIE SEMICONDUCTOR DEVICE PACKAGES AND RELATED ASSEMBLIES
Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first...
2018/0033780 SEMICONDUCTOR DEVICES COMPRISING PROTECTED SIDE SURFACES AND RELATED METHODS
Methods of protecting semiconductor devices may involve cutting partially through a thickness of a semiconductor wafer to form trenches between stacks of...
2018/0033779 CIRCUIT BOARDS AND SEMICONDUCTOR PACKAGES
A circuit board comprises a mother substrate including first and second scribing regions, the first scribing region extending in first direction, the second...
2018/0033778 LIGHT-EMITTING DEVICE
A light-emitting device of an embodiment of the present application comprises light-emitting units; a transparent structure having cavities configured to...
2018/0033777 EMBEDDED STACKED DIE PACKAGES AND RELATED METHODS
Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically...
2018/0033776 STRUCTURES AND METHODS FOR PROVIDING ELECTRICAL ISOLATION IN SEMICONDUCTOR DEVICES
Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate...
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