Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2018/0033724 SEMICONDUCTOR DEVICES INCLUDING ELECTRICALLY ISOLATED PATTERNS AND METHOD OF FABRICATING THE SAME
A method of forming a composite dielectric material can be provided by performing a first deposition cycle to form a first dielectric material and performing a...
2018/0033723 Capacitors with Barrier Dielectric Layers, and Methods of Formation Thereof
A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated...
2018/0033722 COMPARISON CIRCUIT INCLUDING INPUT SAMPLING CAPACITOR AND IMAGE SENSOR INCLUDING THE SAME
A comparison circuit that includes an input sampling capacitor and an image sensor including the same are provided. The comparison circuit includes an...
2018/0033721 Package Structures and Method of Forming the Same
An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least...
2018/0033720 SEMICONDUCTOR DEVICE
A first power supply terminal P is provided with an internal wiring connection portion 31A, an upright portion 31B which is joined to the internal wiring...
2018/0033719 SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second...
2018/0033718 INTERCONNECT STRUCTURE HAVING POWER RAIL STRUCTURE AND RELATED METHOD
Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction...
2018/0033717 VACUUM REACTING FORCE WELDING METHOD AND DEVICE THEREOF
The present invention discloses a vacuum reacting force welding method, comprising the following steps: die-bonding a chip onto a substrate through soldering...
2018/0033716 SINTERED MULTILAYER HEAT SINKS FOR MICROELECTRONIC PACKAGES AND METHODS FOR THE PRODUCTION THEREOF
Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal...
2018/0033715 HIGH CURRENT HIGH POWER SOLID STATE RELAY
A solid state relay includes a source bus and a drain bus. Solid state switches are arranged to switch power from the drain bus to the source bus. A control...
2018/0033714 SUBSTRATE UNIT
Provided is a substrate unit configured to improve heat dissipation efficiency while preventing workability from degrading at the time of assembly. A substrate...
2018/0033713 HEAT TRANSFER PLATE
The invention relates to a method for producing an assembly (1), in particular a power electronics unit, comprising the following steps: providing a component...
2018/0033712 ARRAY SUBSTRATE AND ACTIVATION METHOD FOR TFT ELEMENTS IN ARRAY SUBSTRATE
The invention provides an array substrate and activation method for TFT elements in the array substrate. The array substrate comprises a shielding metal layer...
2018/0033711 Double-Encapsulated Power Semiconductor Module and Method for Producing the Same
One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The...
2018/0033710 ELECTRONIC DEVICE COMPRISING AN ENCAPSULATING BLOCK LOCALLY OF SMALLER THICKNESS
An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation...
2018/0033709 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the...
2018/0033708 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable...
2018/0033707 SELECTIVE METALLIZATION OF AN INTEGRATED CIRCUIT (IC) SUBSTRATE
Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC)...
2018/0033706 SEALING CAP FOR ELECTRONIC COMPONENT
An electronic component cap for producing a package having a sealed region by being bonded to a base, having a brazing material-fused surface to which a...
2018/0033705 Semiconductor Device, Method for Testing a Semiconductor Device and Method for Forming a Semiconductor Device
A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a...
2018/0033704 INSPECTION SYSTEM AND INSPECTION METHOD
An inspection system includes a laser light source, an optical system for laser marking that irradiates a semiconductor device with laser light from a metal...
2018/0033703 SILICON CARBIDE SINGLE CRYSTAL SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING...
A silicon carbide single crystal substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface...
2018/0033702 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over amain surface of a semiconductor...
2018/0033701 METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE
At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second...
2018/0033700 METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT
A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel...
2018/0033699 SEMICONDUCTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME
Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin...
2018/0033698 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The...
2018/0033697 GAS FLOATED WORKPIECE SUPPORTING APPARATUS AND NONCONTACT WORKPIECE SUPPORT METHOD
A gas floated workpiece supporting apparatus includes a gas upward ejector ejecting gas upward, and a gas downward ejector located at an upper side from the...
2018/0033696 SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE
A novel semiconductor device, a semiconductor device with low power consumption, a semiconductor device capable of displaying a high-quality image, or a...
2018/0033695 Semiconductor Die Singulation and Structures Formed Thereby
An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the...
2018/0033694 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method includes thinning a wafer to form a wafer having an annular protruding portion on a peripheral portion thereof by...
2018/0033693 STRUCTURE AND FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a ...
2018/0033692 PREVIOUS LAYER SELF-ALIGNED VIA AND PLUG PATTERNING FOR BACK END OF LINE (BEOL) INTERCONNECTS
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an...
2018/0033691 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal...
2018/0033690 METHOD AND STRUCTURE OF FORMING LOW RESISTANCE INTERCONNECTS
Low resistance interconnect structures containing a combined via level/line level interconnect structure and an overlying line level interconnect structure are...
2018/0033689 Seamless Trench Fill Using Deposition/Etch Techniques
Methods for filing a feature on a substrate surface comprising depositing a conformal nitride film on the substrate surface and at least one feature on the...
2018/0033688 GAP-FILL POLYMER FOR FILLING FINE PATTERN GAPS AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME
A gap-fill polymer for filling fine pattern gaps, which has a low dielectric constant (flow-k) and excellent gap filling properties may consist of a compound...
2018/0033687 STRUCTURE AND FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE
Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor...
2018/0033686 METHOD FOR FORMING CONDUCTIVE STRUCTURE IN SEMICONDUCTOR STRUCTURE
A method for manufacturing a semiconductor structure is provided. The method includes forming a mask layer over a substrate, forming a material layer over the...
2018/0033685 Multi-Patterning to Form Vias with Straight Profiles
A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a...
2018/0033684 ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the...
2018/0033683 REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS
A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one...
2018/0033682 ISOLATION REGIONS FOR SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME
Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first...
2018/0033681 BONDED SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING BONDED SEMICONDUCTOR WAFER
A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed...
2018/0033680 SUBSTRATE BONDING METHOD
A substrate bonding method includes: preparing a first substrate having a first silicon oxide film with a film thickness of 50 nm or more arranged on the first...
2018/0033679 METHOD AND APPARATUS FOR FILLING A GAP
A method and apparatus for filling one or more gaps created during manufacturing of a feature on a substrate by: providing a bottom area of a surface of the...
2018/0033678 Isolation Structure of Semiconductor Device
The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device...
2018/0033677 METHOD FOR PREPARING TRENCH ISOLATION STRUCTURE
A method for preparing a trench isolation structure, which comprises the following steps of: providing a substrate; forming an oxide layer on the substrate;...
2018/0033676 ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF FOR HIGH-VOLTAGE DEVICE IN A HIGH-VOLTAGE BCD PROCESS
The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation...
2018/0033675 Patterned Wafer and Method of Making the Same
A patterned wafer used for production of passive-component chip bodies includes a peripheral end portion and at least one passive-component unit that including...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.