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Patent # Description
2018/0040747 SOLAR CELL AND METHOD FOR MANUFACTURING SOLAR CELL
A solar cell is made which has a first conduction-type crystalline silicon substrate having a texture provided on the surface, and an i-type amorphous silicon...
2018/0040746 PASSIVATION OF LIGHT-RECEIVING SURFACES OF SOLAR CELLS WITH HIGH ENERGY GAP (EG) MATERIALS
Methods of passivating light-receiving surfaces of solar cells with high energy gap (Eg) materials, and the resulting solar cells, are described. In an...
2018/0040745 Solar Photovaltaic Module Rapid Shutdown and Safety System
A photovoltaic (PV) module safety shutdown system includes a module-on switch coupled with a PV module coupled with an alternating current (AC) mains panel...
2018/0040744 METHOD FOR STRUCTURING LAYERS OF OXIDIZABLE MATERIALS BY MEANS OF OXIDATION AND SUBSTRATE HAVING A STRUCTURED...
The present invention relates to a method for structuring layers of oxidisable materials. At least one layer, disposed on a substrate, of an oxidisable...
2018/0040743 SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS
A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped...
2018/0040742 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor...
2018/0040741 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is...
2018/0040740 INTEGRATED CIRCUIT DEVICES AND METHOD OF MANUFACTURING THE SAME
An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a...
2018/0040739 TRANSISTOR AND DISPLAY DEVICE HAVING THE SAME
A transistor includes a gate electrode, a semiconductor layer overlapping the gate electrode, the semiconductor layer including an oxide semiconductor, and a...
2018/0040738 FINFETS with Wrap-Around Silicide and Method Forming the Same
A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having...
2018/0040737 ELECTRONIC DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL
Provided are electronic devices having a two-dimensional (2D) material layer. The electronic device includes an electrode layer that directly contacts an edge...
2018/0040736 THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MAKING SAME
A TFT substrate includes a substrate and a plurality of TFTs on the substrate. Each TFT includes a channel layer, a source electrode and a drain electrode on...
2018/0040735 SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate...
2018/0040734 Semiconductor Device and Method
A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a...
2018/0040733 Semiconductor Device and Methods of Manufacture
A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is...
2018/0040732 Multi-Layer Film Device and Method
A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The...
2018/0040731 SEMICONDUCTOR-ON-INSULATOR WAFER, SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR, AND METHODS FOR THE FORMATION...
A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the...
2018/0040730 FABRICATION OF A STRAINED REGION ON A SUBSTRATE
A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the...
2018/0040729 SEMICONDUCTOR DEVICE COMPRISING A TRANSISTOR CELL INCLUDING A SOURCE CONTACT IN A TRENCH, METHOD FOR...
A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate...
2018/0040728 METHOD AND STRUCTURE FOR REDUCING SWITCHING POWER LOSSES
One embodiment is directed towards a method. The method includes forming a drift region of a first conductivity type above or in a substrate. The substrate has...
2018/0040727 SELF-ALIGNED SHALLOW TRENCH ISOLATION AND DOPING FOR VERTICAL FIN TRANSISTORS
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off...
2018/0040726 NITRIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
In a nitride-semiconductor field-effect transistor, an end on a recess side of a first insulating film is separated by a distance from an opening edge of the...
2018/0040725 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE HAVING A SUPERLATTICE
A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped...
2018/0040724 SEMICONDUCTOR DEVICE INCLUDING RESONANT TUNNELING DIODE STRUCTURE HAVING A SUPERLATTICE
A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor...
2018/0040723 GERMANIUM LATERAL BIPOLAR TRANSISTOR WITH SILICON PASSIVATION
Semiconductor structure including germanium-on-insulator lateral bipolar junction transistors and methods of fabricating the same generally include formation...
2018/0040722 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Provided is a semiconductor device with favorable electrical characteristics. Provided is a semiconductor device with stable electrical characteristics....
2018/0040721 METHOD OF FABRICATING THIN FILM TRANSISTOR STRUCTURE
A method of fabricating a thin film transistor structure is described. An oxide semiconductor layer is fabricated by a self-aligned method and a lift-off...
2018/0040720 FINFET Structure and Method for Fabricating the Same
A method comprises removing a portion of a fin to form a trench over a lower portion of the fin, wherein the lower portion is formed of a first semiconductor...
2018/0040719 PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFET
In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into...
2018/0040718 LASER ANNEALING METHOD, LASER ANNEALING APPARATUS, AND MANUFACTURING PROCESS FOR THIN FILM TRANSISTOR
The present invention provides a laser annealing method for irradiating laser light L to an amorphous silicon thin film deposited on a substrate to obtain...
2018/0040717 LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
The present disclosure relates to a low temperature poly-silicon thin film transistor and a method of preparing the same. The low temperature poly-silicon thin...
2018/0040716 FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR HAVING A CONSISTENT CHANNEL WIDTH
A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate,...
2018/0040715 Metal Gate Formation Through Etch Back Process
A method includes forming a dummy gate stack over a semiconductor region, forming a dielectric layer at a same level as the dummy gate stack, removing the...
2018/0040714 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE WITH ELECTRON MEAN FREE PATH...
A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped...
2018/0040713 FINFET AND METHOD OF FORMING SAME
A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the...
2018/0040712 UNIPOLAR SPACER FORMATION FOR FINFETS
A method for forming a spacer for a semiconductor device includes patterning gate material in a transverse orientation relative to semiconductor fins formed on...
2018/0040711 NONCENTROSYMMETRIC METAL ELECTRODES FOR FERROIC DEVICES
A ferroelectric heterostructure may comprise a ferroelectric layer comprising a ferroelectric material and a first electrode layer comprising a first...
2018/0040710 BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate...
2018/0040709 BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate...
2018/0040708 BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate...
2018/0040707 Semiconductor Devices Utilizing Spacer Structures
Semiconductor devices may include a field insulating layer that is on a substrate, a gate structure that is on the substrate and separated from the field...
2018/0040706 SEMICONDUCTOR DEVICE
In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an...
2018/0040705 Semiconductor Device Structure and Method for Forming the Same
A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a...
2018/0040704 CONTROLLED SYNTHESIS AND TRANSFER OF LARGE AREA HETEROSTRUCTURES MADE OF BILAYER AND MULTILAYER TRANSITION...
Embodiments are presented herein that provide a TMD system wherein the first layered material is made of heterobilayers or multilayers with semiconducting...
2018/0040702 Semiconductor Device and Method
A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An...
2018/0040701 SILICON CARBIDE SEMICONDUCTOR DEVICE
A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface...
2018/0040700 ELECTRONIC DEVICE WITH A GRAPHENE DEVICE AND SEMICONDUCTOR DEVICE FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE
A method for producing an electronic device involves forming a graphene precursor on a first portion of a common semiconductor substrate, forming a graphene...
2018/0040699 METHOD OF FABRICATING SEMICONDUCTOR DEVICES
A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the...
2018/0040698 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes in an active region in which current flows, an n.sup.+-type silicon carbide epitaxial layer of a low concentration and formed...
2018/0040697 FULLY DEPLETED SILICON-ON-INSULATOR DEVICE FORMATION
A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described....
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