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Patent # Description
2018/0040646 TFT Substrate, Display Device And Manufacturing Method
A TFT substrate, a display device and a manufacturing method are disclosed. The TFT substrate includes a substrate and a first TFT structure and a second TFT...
2018/0040645 SEMICONDUCTOR CIRCUIT SUBSTRATE AND DISPLAY DEVICE USING THE SAME
An organic EL display device has a semiconductor circuit substrate comprising a TFT and an organic passivation layer thereon. An AlO layer is formed over the...
2018/0040644 DISPLAY DEVICE AND MANUFACTURING METHOD FOR SAME
Separation of wirings formed on an organic passivation film is prevented in an organic EL display device or a liquid crystal display device. The organic EL...
2018/0040643 ARRAY SUBSTRATE AND DISPLAY DEVICE
An array substrate includes a display region (12), a bonding region (13), and a planarization layer (14), and a thickness of at least a portion of the pattern...
2018/0040642 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a...
2018/0040641 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device having favorable reliability which is capable of retaining data for a long time is provided. The semiconductor device includes a first...
2018/0040640 Display Device and Electronic Device
A display device including a display portion with an extremely high resolution is provided. The display device includes a pixel circuit and a light-emitting...
2018/0040639 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a base substrate, a first thin film transistor disposed on the base substrate, a second thin film transistor disposed on the...
2018/0040638 DISPLAY DEVICE
The disclosure relates to a display device, including a substrate, a plurality of pixels and an electrical circuit. The substrate has a bent portion and a main...
2018/0040637 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are...
2018/0040636 ARRAY SUBSTRATE AND RADIATION DETECTOR
An array substrate according to an embodiment includes a substrate having a first side and a second side, multiple control lines, multiple data lines, a first...
2018/0040635 DISPLAY DEVICE
Provided is a display device, including: a plurality of gate lines extending in a first direction; a plurality of source lines extending in a second direction;...
2018/0040634 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first...
2018/0040633 DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
A display device including a substrate including a display area for displaying an image and a non-display area provided on a side of the display area and...
2018/0040632 Array Substrate and Method of Forming the Same
An array substrate includes a substrate, a buffer layer, a first shielding pattern, a passivation layer, a first semiconductor pattern, a gate insulating...
2018/0040631 METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVING UNIDIRECTIONAL LAYOUT USING SELF-ALIGNED...
At least one method, apparatus and system disclosed involves an integrated circuit comprising a unidirectional metal layout. A first set of metal features are...
2018/0040630 SEMICONDUCTOR DEVICE
According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first...
2018/0040629 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device in accordance with an embodiment may include a cell structure, a source coupling structure, and a source discharge transistor. The cell...
2018/0040628 VERTICAL-TYPE MEMORY DEVICE
A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on...
2018/0040627 RIDGED WORD LINES FOR INCREASING CONTROL GATE LENGTHS IN A THREE-DIMENSIONAL MEMORY DEVICE
After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater...
2018/0040626 Vertical String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor Comprising A...
A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating...
2018/0040625 COMPLEMENTARY SONOS INTEGRATION INTO CMOS FLOW
Methods of integrating complementary SONOS devices into a CMOS process flow are described. The method begins with depositing and patterning a first photoresist...
2018/0040624 REPLACEMENT CONTROL GATE METHODS AND APPARATUSES
Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in...
2018/0040623 THREE-DIMENSIONAL MEMORY DEVICE WITH SEMICIRCULAR METAL-SEMICONDUCTOR ALLOY FLOATING GATE ELECTRODES AND...
Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material...
2018/0040622 SEMICONDUCTOR DEVICES
A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate,...
2018/0040621 Structure and Method for MOSFET Device
The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more...
2018/0040620 INTEGRATED CIRCUIT DEVICES AND METHODS OF FABRICATING SUCH DEVICES
An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an...
2018/0040619 STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench;...
2018/0040618 Semiconductor Devices Having Fin Field Effect Transistor (FinFET) Structures and Manufacturing and Design...
Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed...
2018/0040617 Method and Structure for Gap Filling Improvement
Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a...
2018/0040616 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a substrate first through fourth active fins on the substrate, extending in a first direction, and spaced apart from one...
2018/0040615 Semiconductor Device and Method
A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and...
2018/0040614 Fin Structure and Method of Forming Same
A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second...
2018/0040613 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE STACKS
Structures and formation methods of a semiconductor device are provided. The semiconductor device includes a substrate and a first fin structure and a second...
2018/0040612 SEMICONDUCTOR DEVICE
To improve current detection performance of a sense IGBT particularly in a low current region in a semiconductor device equipped with a main IGBT and the sense...
2018/0040611 CO-INTEGRATION OF SELF-ALIGNED AND NON-SELF ALIGNED HETEROJUNCTION BIPOLAR TRANSISTORS
The present disclosure relates to semiconductor structures and, more particularly, to co-integration of self-aligned and non-self aligned heterojunction...
2018/0040610 DISCRETE CAPACITOR AND MANUFACTURING METHOD THEREOF
A discrete capacitor of the present invention includes a substrate having a front surface portion, an impurity diffusion layer formed on the front surface...
2018/0040609 SEMICONDUCTOR DEVICE
A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one...
2018/0040608 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A semiconductor chip including an internal circuit, a plurality of electrode pads and a plurality of I/O cells. The plurality of electrode pads are arranged on...
2018/0040607 LTPS Display Panel And Manufacturing Method For The Same
A LTPS display panel and manufacturing method for the same. The LTPS display panel includes a color filer, a black matrix located on the color filter and a TFT...
2018/0040606 SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device...
2018/0040605 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD
An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a semiconductor fin located on the semiconductor substrate. The...
2018/0040604 DIODE DESIGN OF FINFET DEVICE
A method for manufacturing an electrostatic discharge (ESD) protection device includes providing a semiconductor structure including a semiconductor substrate...
2018/0040603 SCRs with Checker Board Layouts
An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of...
2018/0040602 LOW-CAPACITANCE ELECTROSTATIC DAMAGE PROTECTION DEVICE AND METHOD OF DESIGNING AND MAKING SAME
An electrostatic discharge (ESD) device includes an active region. The active region includes a first active line having a first plurality of gate features;...
2018/0040601 SEMICONDUCTOR DEVICE AND COMPOSITE SEMICONDUCTOR DEVICE
Provided is a lateral field effect transistor in which response performance is improved. In a lateral field effect transistor, a block is arranged closer to a...
2018/0040600 GOA CIRCUIT BASED ON LTPS SEMICONDUCTOR THIN FILM TRANSISTOR
The present invention provides a GOA circuit based on LTPS semiconductor thin film transistor to control the voltage levels of the first node (Q(n)) and the...
2018/0040598 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed...
2018/0040597 PACKAGING OPTOELECTRONIC COMPONENTS AND CMOS CIRCUITRY USING SILICON-ON-INSULATOR SUBSTRATES FOR PHOTONICS...
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For...
2018/0040596 SEMICONDUCTOR DEVICE, DISPLAY PANEL ASSEMBLY, SEMICONDUCTOR STRUCTURE
A semiconductor device includes a chip, a plurality of first bumps, and a plurality of second bumps. The chip includes an active surface. The first bumps are...
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