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Patent # Description
2018/0040595 COMPOSITE SUBSTRATE AND LIGHT EMITTING DEVICE
The composite substrate includes: a lead frame including one or more pairs of support leads, each of the one or more pairs of support leads including a first...
2018/0040594 LIGHT EMITTING MODULE
A light emitting module including a light emitting device package structure and a heat dissipation structure is provided. The light emitting device package...
2018/0040593 SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES
A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the...
2018/0040592 INTERCONNECT STRUCTURE WITH IMPROVED CONDUCTIVE PROPERTIES AND ASSOCIATED SYSTEMS AND METHODS
Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive...
2018/0040591 INTEGRATED ELECTRONIC DEVICE WITH TRANSCEIVING ANTENNA AND MAGNETIC INTERCONNECTION
An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface,...
2018/0040590 SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A semiconductor package comprising: a substrate including an external connection terminal and a cavity; a first semiconductor chip disposed in the cavity, the...
2018/0040589 MICROELECTRONIC PACKAGES AND ASSEMBLIES WITH REPEATERS
A microelectronic assembly includes a circuit panel having a plurality of first contacts at a major surface thereof. One or more microelectronic packages...
2018/0040588 SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME
A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the...
2018/0040587 Vertical Memory Module Enabled by Fan-Out Redistribution Layer
Vertical memory modules enabled by fan-out redistribution layer(s) (RDLs) are provided. Memory dies may be stacked with each die having a signal pad directed...
2018/0040586 Chip Package Having Die Structures of Different Heights and Method of Forming Same
Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip...
2018/0040585 Package With Thinned Substrate
A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an...
2018/0040584 STACKED IMAGE SENSOR PACKAGE AND STACKED IMAGE SENSOR MODULE INCLUDING THE SAME
Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel...
2018/0040583 METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE
A method of manufacturing a light emitting device includes: preparing a light-transmissive member including a light reflective sheet that has a through-hole,...
2018/0040582 PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a...
2018/0040581 PRESSURE CONTACT TYPE SEMICONDUCTOR DEVICE STACK
To provide a pressure contact type semiconductor device stack which can uniformly pressurize pressure contact type semiconductor devices irrespective of...
2018/0040580 POWER ELECTRONICS MODULE WITH A SUPPORT WITH A PALLADIUM/OXYGEN DIFFUSION BARRIER LAYER AND A SEMICONDUCTOR...
A power electronics module includes a semiconductor element and a support with a functional surface for indirectly connecting to the semiconductor element. A...
2018/0040579 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
The present disclosure provides a semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions...
2018/0040578 Semiconductor Structure and Method of Forming
A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device...
2018/0040577 PAD STRUCTURE AND MANUFACTURING METHOD THEREOF
A pad structure adapted to be disposed on a first package substrate and electrically connected to conductive contacts of a second package substrate includes a...
2018/0040576 DISPLAY DEVICE
A display device including a display panel including a base layer, a circuit layer disposed on the base layer, and a pad part having a plurality of pads...
2018/0040575 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first...
2018/0040574 ELECTRONIC CHIP
An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity...
2018/0040573 CHIP CARRIER AND METHOD THEREOF
A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad,...
2018/0040572 Warpage Balancing in Thin Packages
Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the...
2018/0040571 SEMICONDUCTOR DEVICES
A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer...
2018/0040570 NOISE CANCELLATION FOR A MAGNETICALLY COUPLED COMMUNICATION LINK UTILIZING A LEAD FRAME
An integrated circuit package includes a portion of a lead frame disposed within an encapsulation. The lead frame includes a first conductor including a first...
2018/0040569 SUBSTRATE DESIGNED TO PROVIDE EMI SHIELDING
Packages and packaging techniques for providing EMI shielding are described. In an embodiment, a package includes an electrically conductive ground structure...
2018/0040568 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME
An electronic package is provided, which includes: a carrier; a plurality of electronic elements disposed on the carrier; a barrier frame disposed on the...
2018/0040567 MULTIPLE DRIVER PIN INTEGRATED CIRCUIT STRUCTURE
An integrated circuit (IC) structure includes a plurality of driver pins at a driver pin level and oriented in a driver pin direction. Each layer of a...
2018/0040566 SYSTEM AND METHOD FOR FORMING AND AUTHENTICATING AN INTEGRATED CIRCUIT
A system and method of forming an authenticatable integrated circuit comprising altering a material property of a semiconductor layer of the integrated circuit...
2018/0040565 SEMICONDUCTOR DEVICE
According to one embodiment, the insulating layer is provided on the terrace portions. The plurality of contact portions extend through the insulating layer in...
2018/0040564 SURFACE TREATMENT FOR SEMICONDUCTOR STRUCTURE
A method includes forming a dielectric layer and forming a metallic conductor at least partially in the dielectric layer. Formation of the metallic conductor...
2018/0040563 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using...
2018/0040562 ELEKTRONISCHES MODUL UND VERFAHREN ZU SEINER HERSTELLUNG
The invention relates to an electronic, in particular power-electronic module (28) with a first layer composite (1) which comprises an inner, electrically...
2018/0040561 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines...
2018/0040560 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines...
2018/0040559 Semiconductor Device and Method
A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of depositing a first insulating...
2018/0040558 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality...
2018/0040557 ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a...
2018/0040556 INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE
Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a...
2018/0040555 DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT
Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance:...
2018/0040554 METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH STACKED ANALOG COMPONENTS IN BACK END OF LINE (BEOL) REGIONS
A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first...
2018/0040553 SEMICONDUCTOR MEMORY DEVICE WITH 3D STRUCTURE
A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a...
2018/0040552 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the...
2018/0040551 INTERCONNECT SUBSTRATE HAVING CAVITY FOR STACKABLE SEMICONDUCOTR ASSEMBLY, MANUFACTURING METHOD THEREOF AND...
An interconnect substrate includes vertical connection channels around a cavity. The vertical connection channels are made of a combination of metal posts and...
2018/0040550 METHOD OF FABRICATING ELECTRONIC PACKAGE
A method of fabricating an electronic package is provided, including: providing a carrier body having a first surface formed with a plurality of recessed...
2018/0040549 PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads...
2018/0040548 SEMICONDUCTOR PACKAGE INCLUDING A REWIRING LAYER WITH AN EMBEDDED CHIP
A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The...
2018/0040547 INTERPOSER DEVICE INCLUDING AT LEAST ONE TRANSISTOR AND AT LEAST ONE THROUGH-SUBSTRATE VIA
In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the...
2018/0040546 DENSE REDISTRIBUTION LAYERS IN SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME
A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed...
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