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Patent # Description
2018/0048346 METHODS FOR CONFIGURING RADIO RESOURCES IN A WIRELESS COMMUNICATION SYSTEM AND APPARATUSES
A method may be provided for configuring an up/down link radio resource for a machine type communication (MTC) terminal in 3GPP LTE/LTE-advanced system. The...
2018/0048345 APPARATUS AND METHODS FOR FILTER BYPASS FOR RADIO FREQUENCY FRONT-ENDS
Apparatus and methods for filter bypass for radio frequency front-ends are provided. In certain configurations, filter connectivity of a front-end is changed...
2018/0048344 Radio Frequency Module
A radio frequency module may include a transceiver positioned on a circuit board, a crystal positioned on the circuit board, an antenna positioned on the...
2018/0048343 ELECTRONIC PRIVACY APPARATUS AND RELATED METHODS
An apparatus for enveloping a portable communication or storage device includes a plurality of walls configured to at least partially enclose the portable...
2018/0048342 Protective Mobile Phone Case with Finger Strap
A protective mobile phone case with a finger strap is provided. The case includes a front-facing side, a rear-facing side, longitudinally extending sidewalls,...
2018/0048341 WATCH TYPE MOBILE TERMINAL
The present invention provides a watch type mobile terminal which comprises: a body; a first wireless communication unit installed in the body; a band...
2018/0048340 EQUALIZATION OF RECEIVER
Methods and systems for equalization of a first receiver. A method may include receiving an input signal at the first receiver. The method may also include...
2018/0048339 HARMONIC SELECTIVE FULL-BAND CAPTURE RECEIVER WITH DIGITAL HARMONIC REJECTION CALIBRATION
A receiver includes circuitry configured to determine one or more first local oscillator (LO) harmonics that correspond to one or more first spectrum segments...
2018/0048338 POWER LINE COMMUNICATION METHOD AND DEVICE
Embodiments of the present invention disclose a power line communications device, and the power line communications device includes a USB interface, a protocol...
2018/0048337 System, Method, and Apparatus for Reducing Power Dissipation of Sensor Data on Bit-Serial Communication Interfaces
A communication system receives a binary sequence from a sensor, identifies a power consuming characteristic of the binary sequence, and determines an error...
2018/0048336 DIVERSITY SWITCH CIRCUIT, RADIO-FREQUENCY MODULE, AND COMMUNICATION DEVICE
A diversity switch circuit includes first and second switches. The first switch includes a first common terminal connected to a diversity antenna, a first...
2018/0048335 METHODS AND APPARATUS FOR DECODER PROCESSING FOR JOINT MULTI-USER DETECTION
Methods and apparatus are described for decoder processing. The methods and apparatus determine decoding performance occurring in a decoder having first and...
2018/0048334 OUTPUTTING OF CODEWORD BITS FOR TRANSMISSION PRIOR TO LOADING ALL INPUT BITS
Methods, systems, and devices for outputting of codeword bits for transmission prior to loading all input bits. An example encoder may have multiple encoding...
2018/0048333 DEVICE AND ASSOCIATED METHODOLOY FOR ENCODING AND DECODING OF DATA FOR AN ERASURE CODE
A method of redundantly encoding data includes formatting the data into columns and rows, and generating first and second sets of projections of the data using...
2018/0048332 LOW LATENCY SOFT DECODER ARCHITECTURE FOR GENERALIZED PRODUCT CODES
Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, a system accesses...
2018/0048331 METHOD AND SYSTEM FOR DATA TRANSMISSION
A method and a system for data transmission are provided. The method includes: determining a size of a first block and a first degree distribution for a first...
2018/0048330 LOW DENSITY PARITY CHECK CODE FOR TERRESTRIAL CLOUD BROADCAST
Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density...
2018/0048329 MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF
An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on...
2018/0048328 LDPC PERFORMANCE IMPROVEMENT USING SBE-LBD DECODING METHOD AND LBD COLLISION REDUCTION
Systems and methods are described for performing Layered Belief LDPC decoding on received Standard Belief LDPC encoded data bursts. In on implementation, a...
2018/0048327 SIGMA-DELTA MODULATOR ARRANGEMENT, METHOD AND CONTROL APPARATUS FOR CALIBRATING A CONTINUOUS-TIME SIGMA-DELTA...
A sigma-delta modulator arrangement includes a continuous-time sigma-delta modulator with at least one modulator stage, a digital integrator and a given number...
2018/0048326 TECHNIQUES FOR IMPROVING MISMATCH SHAPING OF DYNAMIC ELEMENT MATCHING CIRCUIT WITHIN DELTA-SIGMA MODULATOR
A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The...
2018/0048325 MULTI-PATH ANALOG FRONT END WITH ADAPTIVE PATH
In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths and a controller. The plurality of...
2018/0048324 METHOD AND APPARATUS FOR ANALOG TO DIGITAL ERROR CONVERSION WITH MULTIPLE SYMMETRIC TRANSFER FUNCTIONS
An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration...
2018/0048323 SYNTHESIZER
A fine-adjustment synthesizer includes a fractional phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a...
2018/0048322 Phase Locked Loop Circuit With Charge Pump Up-Down Current Mismatch Adjustment And Static Phase Error Reduction
A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously...
2018/0048321 DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path...
2018/0048320 SWITCHING POWER CONVERTER
Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage regulation. In certain embodiments, an oscillator...
2018/0048319 DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME
A delay-locked loop (DLL) circuit and an integrated circuit (IC) including the same are provided. The DLL circuit includes a pre-processing circuit configured...
2018/0048318 PULSE-WIDTH MODULATION (PWM) CONTROL LOOP FOR POWER APPLICATION
A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are...
2018/0048317 Configurable Computing-Array Package
The present invention discloses a configurable computing-array package. It comprises a configurable computing die including an array of configurable computing...
2018/0048316 Configurable Computing Array Using Two-Sided Integration
The present invention discloses a configurable computing array using two-sided integration. It is a monolithic integrated circuit comprising at least a...
2018/0048315 Configurable Computing Array Based on Three-Dimensional Vertical Writable Memory
The present invention discloses a configurable computing array. It is a monolithic integrated circuit comprising at least a configurable computing element and...
2018/0048314 Configurable Computing Array
The present invention discloses a configurable computing array. It comprises an array of configurable computing elements and an array of configurable logic...
2018/0048313 Configurable Computing Array Comprising Three-Dimensional Writable Memory
The present invention discloses a configurable computing array comprising three-dimensional writable memory (3D-W). It is a monolithic integrated circuit...
2018/0048312 MULTI-FORMAT DRIVER INTERFACE
A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second...
2018/0048311 Digital Circuits Having Improved Transistors, and Methods Therefor
Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or...
2018/0048310 CALIBRATION CIRCUIT FOR ON-CHIP DRIVE AND ON-DIE TERMINATION
Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive...
2018/0048309 Power Line Communication Smart Relay
A replacement smart relay having a relay, controlled by a microcontroller operably connected through a power line communication line that receives instructions...
2018/0048308 SWITCH CIRCUIT, RADIO-FREQUENCY MODULE, AND COMMUNICATION DEVICE
A switch circuit includes first and second switches. The first switch includes a first common terminal and at least two first selection terminals selectively...
2018/0048307 LOW-VOLTAGE HIGH-SPEED RECEIVER
A line receiver is described. The line receiver may be configured to receive signals transmitted via a communication channel, such as a metal trace on a...
2018/0048306 POWER CIRCUIT AND POWER MODULE USING MISFET HAVING CONTROL CIRCUIT DISPOSED BETWEEN GATE AND SOURCE
The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a...
2018/0048305 RADIO-FREQUENCY SWITCH WITH SWITCHABLE CAPACITOR
Radio-frequency switch with switchable capacitor. In some embodiments, a RF switch includes a first field-effect transistor (FET) disposed between an input...
2018/0048304 SEMICONDUCTOR SWITCHING STRING
A semiconductor switching string including a series-connected switching assemblies. Each assembly has a main switching element including first and second...
2018/0048303 SWITCHING DEVICE FOR OPERATING AT LEAST ONE LOAD
Switching device (1) for operating at least one load, comprising at least one switching unit (7; 8; 9), which switches a tapped current phase (L) to a load...
2018/0048302 DRIVE CIRCUIT AND SEMICONDUCTOR DEVICE
A drive circuit includes one constant voltage circuit for generating a first voltage and a second voltage, a first output circuit connected to the constant...
2018/0048301 Method And System For Reliable Bootstrapping Switches
Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch...
2018/0048300 ACTIVE TRIAC TRIGGERING CIRCUIT
A power supply unit for use with thermostats or other like devices requiring power. A power supply unit may be designed to keep electromagnetic interference...
2018/0048299 HIGH-VOLTAGE PULSE GENERATOR
A high-voltage pulse generator including a plurality of stages and an electrode for returning current to ground, connected in series, each of the stages...
2018/0048298 Current-controlled CMOS logic family
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process...
2018/0048297 Phase-Inverted Clock Generation Circuit and Register
A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first...
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