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Patent # Description
2018/0053734 SEMICONDUCTOR CHIP WITH ANTI-REVERSE ENGINEERING FUNCTION
A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the...
2018/0053733 PREVENTION OF REVERSE ENGINEERING OF SECURITY CHIPS
A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric...
2018/0053732 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a semiconductor chip disposed in a through-hole of a first connection member having the through-hole and a second...
2018/0053731 INVISIBLE COMPARTMENT SHIELDING
A method for shielding a compartment in a module of an electronic device includes molding the module using a mold material that activates when a laser is...
2018/0053730 Semiconductor Packages and Methods of Forming the Same
Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of...
2018/0053729 ALIGNMENT MARK STRUCTURE WITH DUMMY PATTERN
An alignment mark structure including a substrate, an alignment mark and at least one dummy pattern is provided. The alignment mark is disposed on the...
2018/0053728 FORMATION OF ADVANCED INTERCONNECTS
An advanced metal conductor structure is described. An integrated circuit device including a substrate with a patterned dielectric layer. The pattern includes...
2018/0053727 FORMATION OF ADVANCED INTERCONNECTS
An integrated circuit device includes a substrate including a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of...
2018/0053726 NITRIDIZED RUTHENIUM LAYER FOR FORMATION OF COBALT INTERCONNECTS
An advanced metal conductor structure is described. An integrated circuit device including a substrate having a dielectric layer is patterned. The pattern...
2018/0053725 FORMATION OF ADVANCED INTERCONNECTS
A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. The set of...
2018/0053724 NITRIDIZED RUTHENIUM LAYER FOR FORMATION OF COBALT INTERCONNECTS
An advanced metal conductor structure and a method for constructing the structure are described. A pattern is provided in a dielectric layer. The pattern...
2018/0053723 PACKAGE STRUCTURE HAVING EMBEDDED BONDING FILM AND MANUFACTURING METHOD THEREOF
A package structure having an embedded bonding film including a redistribution substrate, a bonding film and a core is provided. The redistribution substrate...
2018/0053722 SINGLE-SIDED POWER DEVICE PACKAGE
In some examples, a circuit package further includes an insulating layer and a first transistor extending through the insulating layer, where the first...
2018/0053720 ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a...
2018/0053719 SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE MODULE USING THE SAME
A semiconductor package includes a frame having a through hole, an electronic component disposed in the through hole, a metal layer disposed on either one or...
2018/0053718 LAYER STACKING STRUCTURE, ARRAY SUBSTRATE AND DISPLAY DEVICE
A layer stacking structure, an array substrate including the layer stacking structure and a display device including the array substrate are provided. The...
2018/0053717 MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR PACKAGE INTERCONNECT
A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal...
2018/0053716 METHOD AND STRUCTURE TO FABRICATE A NANOPOROUS MEMBRANE
A self-assembled heteroepitaxial oxide nanocomposite film including alternating layers of a first metal oxide having a first melting point and a second metal...
2018/0053715 PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD
A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on a first surface side of the...
2018/0053714 MULTI-LAYER ELECTRICAL CONTACT ELEMENT
Multi-layer electrical contact elements include a flash palladium layer and an intermediate layer of binary hard silver/tin alloy having good corrosion...
2018/0053713 SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD
A semiconductor device includes: a semiconductor die having first and second opposite surfaces, a die pad having the first surface of the semiconductor die...
2018/0053712 HOLES AND DIMPLES TO CONTROL SOLDER FLOW
A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface...
2018/0053711 INTEGRATED DIE PADDLE STRUCTURES FOR BOTTOM TERMINATED COMPONENTS
Bottom terminated components and methods of making bottom terminated components are provided. The bottom terminated component includes a die paddle and at...
2018/0053710 PROCESS FOR MANUFACTURING A SURFACE-MOUNT SEMICONDUCTOR DEVICE, AND CORRESPONDING SEMICONDUCTOR DEVICE
A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal...
2018/0053709 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES, AND CORRESPONDING DEVICE
Semiconductor devices comprising at least one electrically conductive metal element in a non-conductive package material are manufactured by: providing a first...
2018/0053708 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A...
2018/0053707 INTEGRATED CIRCUITS WITH PELTIER COOLING PROVIDED BY BACK-END WIRING
A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more...
2018/0053706 CERAMIC WAFER AND THE MANUFACTURING METHOD THEREOF
A method of producing ceramic wafer includes a forming step and processing step. The processing step includes forming positioning notch or positioning, flat...
2018/0053705 SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate, an...
2018/0053704 PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN PLACE OF A LOW-RESISTIVITY...
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed...
2018/0053703 EPOXY RESIN COMPOSITION FOR SEALING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE SEALED BY USING SAME
An epoxy resin composition for sealing a semiconductor device, of the present invention, contains an inorganic filler, and the inorganic filler contains a...
2018/0053702 3D Printed Hermetic Package Assembly and Method
A method is provided. The method includes one or more of removing existing ball bonds from an extracted die, placing the extracted die into a recess of a...
2018/0053701 Fabrication Method Of Semiconductor Film, Semiconductor Film, And Field Effect Transistor
The present invention provides a semiconductor film, a field effect transistor, and a method of fabricating the semiconductor film that has one or two or more...
2018/0053700 SEMICONDUCTOR MODULE
A semiconductor module is provided in which a semiconductor element is mounted and a plurality of outside connecting modules are drawn from a side of a mold...
2018/0053699 INTEGRATED CIRCUIT DIE HAVING A SPLIT SOLDER PAD
The invention relates to an electronic system comprising: an integrated circuit die having: at least 2 bond pads a redistribution layer, said redistribution...
2018/0053698 SYSTEM AND METHOD FOR CHARACTERIZING CRITICAL PARAMETERS RESULTING FROM A SEMICONDUCTOR DEVICE FABRICATION PROCESS
A system includes three related structures. A first structure includes a first finger interposed between a first pair of sidewalls. The first finger has a...
2018/0053697 Semiconductor Structure and Method for Forming the Same
A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of:...
2018/0053696 DAMAGING COMPONENTS WITH DEFECTIVE ELECTRICAL COUPLINGS
A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple,...
2018/0053695 SYSTEM AND METHOD FOR MEASURING AND IMPROVING OVERLAY USING ELECTRONIC MICROSCOPIC IMAGING AND DIGITAL PROCESSING
An SEM image is acquired. The SEM image shows a metal line and a via hole disposed above the metal line. The via hole exposes a portion of the metal line...
2018/0053694 MULTI-LAYER FILLED GATE CUT TO PREVENT POWER RAIL SHORTING TO GATE STRUCTURE
A method of forming a power rail to semiconductor devices that includes forming a gate structure extending from a first active region to a second active region...
2018/0053693 WIMPY DEVICE BY SELECTIVE LASER ANNEALING
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form...
2018/0053692 WIMPY DEVICE BY SELECTIVE LASER ANNEALING
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form...
2018/0053691 WIMPY DEVICE BY SELECTIVE LASER ANNEALING
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form...
2018/0053690 HORIZONTAL NANOSHEET FETS AND METHOD OF MANUFACTURING THE SAME
Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet...
2018/0053689 PRECLEAN METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECT FABRICATION
A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and...
2018/0053688 METHOD OF METAL FILLING RECESSED FEATURES IN A SUBSTRATE
A method of void-less metal filling of recessed features in a substrate is provided. The method includes providing a substrate containing recessed features...
2018/0053687 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes forming a metal film including Cu on a substrate, forming a protective film on the metal film, forming...
2018/0053686 SEMICONDUCTOR DEVICES
A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode...
2018/0053685 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a...
2018/0053684 METHOD FOR TRANSFERRING SEMICONDUCTOR STRUCTURE
A method for transferring a semiconductor structure is provided. The method includes: coating an adhesive layer onto a carrier substrate; disposing the...
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