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Patent # Description
2018/0053582 CABLE WITH ADAPTED STRANDING
The present disclosure relates to a cable. An exemplary embodiment of the cable (2) comprises a plurality of conductors, wherein the conductors form several...
2018/0053581 Insulation System For An Electrical Machine
The present disclosure relates to insulation systems. The teachings thereof may be embodied in an insulation system for an electrical machine. For example, an...
2018/0053580 LOW-DIELECTRIC CONSTANT POLYIMIDE INSULATION COATING AND ENAMELED WIRE
Provided is a polyimide insulation coating, which is prepared by reacting a diacid anhydride compound represented by Formula (I) with a diamine compound...
2018/0053579 Method of Removing Impurities from Natural Ester, Oil-Based Dielectric Fluids
The method of manufacturing a natural ester, oil-based electrical insulation fluid by contacting refined, bleached, optionally winterized, and deodorized...
2018/0053578 COMPOSITIONS COMPRISING FREE-STANDING TWO-DIMENSIONAL NANOCRYSTALS
The present invention is directed to compositions comprising at least one layer or at least two layers, each layer comprising a substantially two-dimensional...
2018/0053577 ELECTRO-CONDUCTIVE PASTES COMPRISING AN OXIDE ADDITIVE
In general, the present invention relates to an electro-conductive paste comprising an oxide additive and solar cells obtainable therefrom. More specifically,...
2018/0053576 MANIFOLD SYSTEM FOR THE VENTILATED STORAGE OF HIGH LEVEL WASTE AND A METHOD OF USING THE SAME TO STORE HIGH...
A system and method for storing multiple canisters containing high level waste below grade that afford adequate ventilation of the spent fuel storage cavity....
2018/0053575 TRITIUM HOUSING
A tritium housing includes a body extending from a first end to a second end to define a hollow extending therebetween. A lens is disposed adjacent and...
2018/0053574 METHOD AND APPARATUS FOR PREPARING SPENT NUCLEAR FUEL FOR DRY STORAGE
A system and method for drying cavities containing spent nuclear fuel is devised. The invention utilizes a non-intrusive procedure that is based on monitoring...
2018/0053573 INSULATED SOLUTION INJECTOR, SYSTEM INCLUDING THE SAME, AND METHOD OF INJECTING USING THE SAME
An insulated solution injector may include an outer tube and an inner tube arranged within the outer tube. The outer tube and the inner tube may define an...
2018/0053572 REMOTELY OPERATED VEHICLES, SYSTEMS, AND METHODS FOR INSPECTING CORE SHROUDS
A remotely operated vehicle (ROV) for inspecting a core shroud having an outer surface may include: a body configured to be operatively connected to a tether;...
2018/0053571 PWR DECAY HEAT REMOVAL SYSTEM IN WHICH STEAM FROM THE PRESSURIZER DRIVES A TURBINE WHICH DRIVES A PUMP TO...
In conjunction with a pressurized water reactor (PWR) and a pressurizer configured to control pressure in the reactor pressure vessel, a decay heat removal...
2018/0053570 MODULAR COMPRESSION CHAMBER
Examples of a modular compression chamber for use in a compression system are disclosed. The modular compression chamber comprises a plurality of individual...
2018/0053569 DRAM Refresh Method, Apparatus, and System
A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to...
2018/0053568 NAND FLASH MEMORY AND READING METHOD THEREOF
An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a...
2018/0053567 SEMICONDUCTOR DEVICES, SEMICONDUCTOR SYSTEMS, AND METHODS THEREOF
A semiconductor system may be provided. The semiconductor system may include a first semiconductor device, a second semiconductor device, and a third...
2018/0053566 BUILT-IN SELF-TEST (BIST) ENGINE CONFIGURED TO STORE A PER PATTERN BASED FAIL STATUS IN A PATTERN MASK REGISTER
A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes...
2018/0053565 MEMORY SYSTEM AND OPERATING METHOD FOR THE SAME
A memory system comprises a memory device including a plurality of memory blocks, the memory device being configured to perform a program operation and a...
2018/0053564 CURRENT SAMPLING AND HOLDING CIRCUIT AND SIGNAL ACQUISITION SYSTEM
A current sampling and holding circuit is disclosed. The current sampling and holding circuit includes: a canceling circuit, connected in series between a VDD...
2018/0053563 CIRCUIT FOR GENERATING BIAS CURRENT FOR READING OTP CELL AND CONTROL METHOD THEREOF
Provided is a circuit for generating a bias current, which includes a current generation unit including a plurality of current mirrors that generate a...
2018/0053562 NON-VOLATILE MEMORY WITH READ DISTURB DETECTION FOR OPEN BLOCKS
A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block...
2018/0053561 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device according to the present invention includes a first memory cell, a second memory cell, a dummy transistor, and a voltage control...
2018/0053560 Method And Apparatus For Configuring Array Columns And Rows For Accessing Flash Memory Cells
In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash...
2018/0053559 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
A semiconductor memory device includes a first word line and a second word line that are adjacent to each other, a first voltage boosting circuit configured to...
2018/0053558 THREE DIMENSIONAL MEMORY DEVICE WITH ACCESS SIGNAL TRIGGERING FROM VOLTAGE PUMP OUTPUT LEVELS
A method is described. The method includes, within a semiconductor memory device comprising a three dimensional storage cell array, pumping a voltage and...
2018/0053557 SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY CONFIGURED TO SWITCH BETWEEN A REFERENCE CURRENT READING...
The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area...
2018/0053556 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a first circuit configured to process data received from and transmitted to an external controller, a second circuit...
2018/0053555 PROGRAMMING NONVOLATILE MEMORY CELLS USING RESOLUTION-BASED AND LEVEL-BASED VOLTAGE INCREMENTS
Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In...
2018/0053554 NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND READING METHOD OF NONVOLATILE...
A nonvolatile memory device includes a memory cell array and a row decoder circuit. The row decoder circuit turns on memory cells of a plurality of cell...
2018/0053553 Method And Apparatus For Configuring Array Columns And Rows For Accessing Flash Memory Cells
In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash...
2018/0053552 SEGMENTED MEMORY AND OPERATION
Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is...
2018/0053551 ALL-OPTICAL SINGLE-ATOM PHOTON ROUTER CONTROLLED BY A SINGLE PHOTON
A switch activated by a single control photon for routing a single target photon from either of two switch inputs to either of two switch outputs. The device...
2018/0053550 LOW POWER ANALOG OR MULTI-LEVEL MEMORY FOR NEUROMORPHIC COMPUTING
A neuron circuit for use in a neural network is disclosed. The neural network includes a plurality of field effect transistors having confined channels. The...
2018/0053549 RESISTIVE MEMORY AND MEMORY CELL
A memory unit is provided. The memory unit includes a resistive element, a diode, and a first transistor. The resistive element has a first terminal receiving...
2018/0053548 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality...
2018/0053547 AUTONOMOUS DEVICE FOR DETECTING CHARACTERISTICS OF A MEDIUM TO BE MEASURED AND METHOD THEREFOR
An autonomous device for detecting characteristics of a medium to be measured is disclosed. The device includes a sensor, a first microcontroller and a second...
2018/0053546 SEMICONDUCTOR DEVICE, TEST PROGRAM, AND TEST METHOD
When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of...
2018/0053545 SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING THE SAME
A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The...
2018/0053544 MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DATA INTERFACES
A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant...
2018/0053543 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device having improved...
2018/0053541 SEMICONDUCTOR MEMORY APPARATUS
A semiconductor memory apparatus may be provided. The semiconductor memory apparatus may include a row decoder configured to generate one or more row decoding...
2018/0053540 On-Die Termination of Address and Command Signals
A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and...
2018/0053539 SEMICONDUCTOR DEVICE AND METHOD OF OPERATING AND CONTROLLING A SEMICONDUCTOR DEVICE
An exemplary embodiment includes a method of controlling a semiconductor device. The semiconductor device includes a memory cell array including a plurality of...
2018/0053538 APPARATUSES AND METHODS FOR ADJUSTING DELAY OF COMMAND SIGNAL PATH
Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a...
2018/0053537 MEMORY MACRO AND METHOD OF OPERATING THE SAME
A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of...
2018/0053536 Bitline Sensing Latch
A bit line sensing latch circuit is disclosed. In one embodiment, a latch circuit includes a keeper and a precharge circuit. The keeper may be implemented...
2018/0053535 MEMORY DEVICE AND CENTRAL PROCESSING UNIT
A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data...
2018/0053534 BASE UNIT AND DISK DRIVE APPARATUS
A base member includes a recessed portion arranged to extend in radial directions and recessed upward from a lower surface of the base member, the radial...
2018/0053533 THERMALLY CONDUCTIVE AND VIBRATION DAMPING ELECTRONIC DEVICE ENCLOSURE AND MOUNTING
A system and method for heat dissipation and vibration damping of electronic devices in which an assembly is formed by one or more surfaces comprised of at...
2018/0053532 MULTI-SOURCE VIDEO INPUT
A method of merging video files into a consolidated video file includes receiving, by a computer device, plural video files from plural video capture devices....
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