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Patent # Description
2018/0061790 ELECTRONIC STRUCTURE PROCESS
An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding...
2018/0061789 ELECTRONIC STRUCTURE, AND ELECTRONIC STRUCTURE ARRAY
An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is...
2018/0061788 CHIP PACKAGE ARRAY, AND CHIP PACKAGE
A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array....
2018/0061787 Semiconductor Package
A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a...
2018/0061786 SEMICONDUCTOR PACKAGE INTEGRATED WITH MEMORY DIE
A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio...
2018/0061785 POWER TRANSISTOR WITH HARMONIC CONTROL
A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to...
2018/0061784 MULTI-DIE INTEGRATED CIRCUIT DEVICE WITH CAPACITIVE OVERVOLTAGE PROTECTION
An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first...
2018/0061783 Lid Structure for a Semiconductor Device Package and Method for Forming the Same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure...
2018/0061782 ACTIVATING REACTIONS IN INTEGRATED CIRCUITS THROUGH ELECTRICAL DISCHARGE
Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated...
2018/0061780 ACTIVE TAMPER DETECTION CIRCUIT WITH BYPASS DETECTION AND METHOD THEREFOR
An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector...
2018/0061779 SEMICONDUCTOR DEVICE
A semiconductor device includes a first substrate, a second substrate, a first pad, a second pad, a first micro-bump, a first resin layer, and an insulating...
2018/0061778 PACKAGING FOR HIGH SPEED CHIP TO CHIP COMMUNICATION
Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip...
2018/0061777 TILED-STRESS-ALLEVIATING PAD STRUCTURE
Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad...
2018/0061776 SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the...
2018/0061775 LOW PROFILE PASSIVE ON GLASS (PoG) DEVICE COMPRISING A DIE
A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to...
2018/0061774 Wire Bond Wires for Interference Shielding
Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an...
2018/0061773 REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS
Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may...
2018/0061772 Semiconductor Lithography Alignment Feature with Epitaxy Blocker
A type III-V semiconductor substrate is provided. Semiconductor material is removed from the type III-V semiconductor substrate such that the type III-V...
2018/0061771 SURFACE TREATMENT FOR SEMICONDUCTOR STRUCTURE
A method includes forming a dielectric layer and forming a metallic conductor at least partially in the dielectric layer. Formation of the metallic conductor...
2018/0061770 METAL ALLOY CAPPING LAYERS FOR METALLIC INTERCONNECT STRUCTURES
A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the...
2018/0061769 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An interlayer insulating film has via holes. A sidewall conductive layer is arranged along a sidewall surface of one via hole and contains one or more kinds...
2018/0061768 COBALT FIRST LAYER ADVANCED METALLIZATION FOR INTERCONNECTS
A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of...
2018/0061767 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package structure includes a semiconductor substrate, at least one semiconductor die, an encapsulant, a protection layer, a plurality of...
2018/0061766 SEMICONDUCTOR DEVICES ON TWO SIDES OF AN ISOLATION LAYER
An integrated circuit device includes only semiconductor devices with a same first polarity on one side of an insulator layer and only semiconductor devices...
2018/0061765 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes a first wiring structure and a second wiring structure having a higher wiring density. The second wiring structure includes a...
2018/0061764 Standard Cell Layout for Better Routability
A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using...
2018/0061763 DEVICE PERFORMANCE IMPROVEMENT USING BACKSIDE METALLIZATION IN A LAYER TRANSFER PROCESS
A silicon-on-insulator (SOI) device includes an active layer including active, devices, such as transistors. Below the active layer is an insulating layer,...
2018/0061762 SEMICONDUCTOR DEVICE WITH REDUCED CONTACT RESISTANCE
An interconnect structure and methods of forming the interconnect structure an interconnect dielectric including at least one contact landing within the...
2018/0061761 LOW ASPECT RATIO INTERCONNECT
A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes...
2018/0061760 SUBSTRATE CONTACT USING DUAL SIDED SILICIDATION
An integrated circuit device may include a front-side contact coupled to a front-side metallization. The integrated circuit device may further include a...
2018/0061759 VERTICAL FUSE STRUCTURES
Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein...
2018/0061758 VERTICAL FUSE STRUCTURES
Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein...
2018/0061757 VERTICAL FUSE STRUCTURES
Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein...
2018/0061756 ONE TIME PROGRAMMABLE MEMORY CELL AND MEMORY ARRAY
One time programmable memory cell and memory array Memory cells and corresponding memory arrays are provided. The memory cell comprises a fusable element and a...
2018/0061755 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate comprising an upper layer portion, a first insulating member located in the upper layer portion of...
2018/0061754 AVOIDING GATE METAL VIA SHORTING TO SOURCE OR DRAIN CONTACTS
Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer....
2018/0061753 INTERCONNECT STRUCTURE AND METHODS THEREOF
A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a...
2018/0061752 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a capacitor is formed on the substrate and a hard mask on the...
2018/0061751 ELECTRONIC COMPONENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE
An electronic component mounting substrate includes an insulating base having a rectangular shape in plan view and including a first main surface, a second...
2018/0061750 METAL SILICATE SPACERS FOR FULLY ALIGNED VIAS
A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or...
2018/0061749 POST ZERO VIA LAYER KEEP OUT ZONE OVER THROUGH SILICON VIA REDUCING BEOL PUMPING EFFECTS
An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A...
2018/0061748 SEMICONDUCTOR CHIP, DISPLAY PANEL, AND ELECTRONIC DEVICE
A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more...
2018/0061747 PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
A package structure is provided, including a carrier, an electronic component disposed on the carrier and having a sensing area, an encapsulant formed on the...
2018/0061746 LEAD FRAME AND ELECTRONIC COMPONENT DEVICE
An electronic component device, includes: a lead frame including a terminal portion, the terminal portion including a columnar electrode and a metal plating...
2018/0061745 Semiconductor Chip Package Having a Repeating Footprint Pattern
A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First...
2018/0061744 HIGH-POWER ACOUSTIC DEVICE WITH IMPROVED PERFORMANCE
The present disclosure relates to a high-power acoustic device with improved performance. The disclosed acoustic device includes a substrate, a die-attach...
2018/0061743 Flexible Circuit Substrate With Temporary Supports and Equalized Lateral Expansion
An item may have a flexible support structure and may include a flexible component. The flexible component may have electrical components mounted on component...
2018/0061742 Semiconductor Devices and Methods for Forming a Semiconductor Device
A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond...
2018/0061741 SEMICONDUCTOR DIE PACKAGE AND METHOD OF PRODUCING THE PACKAGE
A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in...
2018/0061740 ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME
An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as...
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