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Patent # Description
2018/0076228 ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE...
Embodiments of the present invention provides an array substrate. The array substrate includes a display region and a packaging region. The packaging region...
2018/0076227 EMBEDDED SECURITY CIRCUIT FORMED BY DIRECTED SELF-ASSEMBLY
Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set...
2018/0076226 ASYMMETRIC BAND GAP JUNCTIONS IN NARROW BAND GAP MOSFET
A semiconductor device with one or more fin structures formed from a first material, gate, source, and drain regions formed from a second material, and a...
2018/0076225 Sub-Fin Removal for SOI Like Isolation with Uniform Active Fin Height
Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial...
2018/0076224 PIXEL STRUCTURE AND RELATED FABRICATION METHOD
A pixel structure includes a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer. The second metal layer is...
2018/0076223 DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS
A display substrate, a display apparatus and a production method of the display substrate are provided. The display substrate includes a plurality of pixel...
2018/0076222 CAVITY FORMATION USING SACRIFICIAL MATERIAL
A method for fabricating a semiconductor device involves providing a semiconductor substrate, forming an oxide layer in the semiconductor substrate, forming a...
2018/0076221 DISPLAY DEVICE
Layers on a resin substrate in a peripheral area include wires extending in a wiring direction, and an inorganic insulating layer. The inorganic insulating...
2018/0076220 CONDUCTIVE CONTACTS IN SEMICONDUCTOR ON INSULATOR SUBSTRATE
A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A...
2018/0076219 METHOD AND DEVICE FOR SYNTHESIZING A CIRCUIT LAYOUT
A method for synthesizing a circuit layout, characterized by the following features: primary circuit functions are placed on the circuit layout; secondary...
2018/0076218 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
There is provided a semiconductor device. The semiconductor device includes a source layer, a well pickup layer formed on the source layer, a body structure...
2018/0076217 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a...
2018/0076216 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a columnar member, and an insulating film. The stacked body is...
2018/0076215 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
According to one embodiment, a semiconductor memory device includes a substrate, interconnect portions, a conductive layer, a stacked body, and columnar...
2018/0076213 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and...
2018/0076212 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor...
2018/0076211 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first...
2018/0076210 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a base semiconductor layer, first and second conductive layers, a semiconductor body, a...
2018/0076209 Integrated Assemblies and Methods of Forming Integrated Assemblies
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces...
2018/0076208 SEMICONDUCTOR DEVICE
The semiconductor device according to the embodiments comprises: a plurality of first conductive layers arranged in a first direction above a substrate, the...
2018/0076207 MASK ROM AND PROCESS FOR FABRICATING THE SAME
A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each...
2018/0076206 SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF
The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A control gate electrode is formed over a semiconductor...
2018/0076205 SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells...
2018/0076204 MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used...
2018/0076203 Structure and Method for Semiconductor Device
A semiconductor device includes a substrate; an isolation structure over the substrate; and two fins in a first region of the semiconductor device extending...
2018/0076202 FinFET CMOS WITH SILICON FIN N-CHANNEL FET AND SILICON GERMANIUM FIN P-CHANNEL FET
A substrate having a silicon region and a silicon germanium region is provided. A first set of fins in the silicon region and a second set of fins in the...
2018/0076201 SEMICONDUCTOR DEVICE
A semiconductor device includes a lateral MOSFET and a vertical semiconductor device that are formed on the same semiconductor substrate. In the lateral...
2018/0076200 FinFET CMOS WITH SILICON FIN N-CHANNEL FET AND SILICON GERMANIUM FIN P-CHANNEL FET
An advanced FinFET structure is described. A FinFET device includes a set of n-type FinFET devices and a set of p-type FinFET devices disposed on a substrate....
2018/0076199 COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR CIRCUIT HAVING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND METHOD...
A complimentary metal-oxide-semiconductor (CMOS) circuit including: a substrate; and a plurality of field-effect transistors on the substrate. Each of the...
2018/0076198 Techniques Providing Metal Gate Devices with Multiple Barrier Layers
A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain...
2018/0076197 SEMICONDUCTOR DEVICES EMPLOYING FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE CHANNEL STRUCTURES WITHOUT...
Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical...
2018/0076196 DIODE
A diode according to the present invention includes a semiconductor layer of a first conductivity type having an impurity concentration of 1.times.10.sup.16...
2018/0076195 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE
Provided is a semiconductor device that occupies a small area, a highly integrated semiconductor device, or a semiconductor device with high productivity. To...
2018/0076194 TRANSISTOR FOR INCREASING A RANGE OF A SWING OF A SIGNAL
A transistor includes a first doping well, a second doping well, a first doping area, a second doping area, a gate layer, and at least one compensation...
2018/0076193 SEMICONDUCTOR DEVICE
An RC-IGBT has a chip area of the semiconductor chip larger than that of a semiconductor chip including an IGBT section but not including an FWD section, as it...
2018/0076192 ELECTROSTATIC PROTECTION DIODE AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING ELECTROSTATIC PROTECTION...
An organic light emitting display device includes a substrate including a pixel region and a peripheral region, a first wiring, a second wiring, a third...
2018/0076191 SEMICONDUCTOR DEVICE
In a semiconductor device including a resistance element, an electrostatic protection element, including a parasitic bipolar transistor having the resistance...
2018/0076190 SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD OF USING
A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a...
2018/0076189 MINIMUM TRACK STANDARD CELL CIRCUITS FOR REDUCED AREA
Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio...
2018/0076188 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFORE
Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first...
2018/0076187 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at...
2018/0076186 SEMICONDUCTOR MEMORY SYSTEM
According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a...
2018/0076185 METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE
A method for fabricating a semiconductor package is provided. Semiconductor dice are disposed on a top surface of a carrier. Each of the semiconductor dice has...
2018/0076184 Semiconductor Packages having Dummy Connectors and Methods of Forming Same
An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit...
2018/0076183 LIGHT EMITTING DEVICE PACKAGE AND LIGHT EMITTING DEVICE PACKAGE MODULE
Disclosed herein is a light emitting device package and a light emitting device package module. The light emitting device package includes: a base including a...
2018/0076182 DISPLAY DEVICES
A display device is provided. The display device includes a substrate having a surface including a display area and a non-display area adjacent to the display...
2018/0076181 LIGHT SOURCE DEVICE AND LIGHT EMITTING APPARATUS
There is provided a light source device which includes at least one kind of light emitting elements of which the number is one or more, and a phosphor excited...
2018/0076180 SEMICONDUCTOR DEVICE HAVING STACKED CHIPS
A semiconductor device includes a first chip having a first via and a second via through the first chip; and a second chip provided on the first chip and...
2018/0076179 STACKED TYPE CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A stacked-type chip package structure includes a first chip, first terminals, a first redistribution layer, a first encapsulant, a second chip, second...
2018/0076178 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and...
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