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Patent # Description
2018/0197884 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes...
2018/0197883 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
An array substrate is provided, which includes: a base substrate; a plurality of gate lines, a plurality of data lines and a plurality of common electrode...
2018/0197882 FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK...
Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX...
2018/0197881 ELECTRONIC COMPONENT HAVING FIELD EFFECT TRANSISTOR CELLS
An electronic component made up of field-effect transistor (FET) cells is disclosed. Each FET cell includes a finger region having drain, gate, and source...
2018/0197880 MULTI-LEVEL FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor...
2018/0197879 MULTI-LEVEL FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor...
2018/0197878 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality...
2018/0197877 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film,...
2018/0197876 THREE-DIMENSIONAL MEMORY DEVICE WITH ENHANCED MECHANICAL STABILITY SEMICONDUCTOR PEDESTAL AND METHOD OF MAKING...
After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack,...
2018/0197875 NONVOLATILE MEMORY WITH ERASE GATE REGION
A nonvolatile memory (NVM) cell includes a semiconductor substrate having a first OD region and a second OD region for forming an erase gate (EG) region. The...
2018/0197874 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
The semiconductor device includes a base material, a plurality of electrode layers, and a first contact portion. The plurality of electrode layers are provided...
2018/0197873 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating...
2018/0197872 NON-VOLATILE MEMORY
A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a...
2018/0197871 FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF
Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a...
2018/0197870 Memory Cells and Methods of Forming a Capacitor
A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second...
2018/0197869 Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in...
2018/0197868 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method thereof include providing a substrate including an active region of a conductivity type and an isolation...
2018/0197867 SEMICONDUCTOR MEMORY DEVICES HAVING AN UNDERCUT SOURCE/DRAIN REGION
A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin...
2018/0197866 SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME, MEMORY CELL HAVING THE...
A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a...
2018/0197865 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of...
2018/0197864 Memory Cells, Arrays Of Two Transistor-One Capacitor Memory Cells, Methods Of Forming An Array Of Two...
A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and...
2018/0197863 METHOD FOR FABRICATING CAPACITOR
A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on...
2018/0197862 Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array...
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material....
2018/0197861 SEMICONDUCTOR DEVICES INCLUDING VARIED DEPTH RECESSES FOR CONTACTS
A first conductivity type finFET device can include first embedded sources/drains of a first material that have a first etch rate. The first embedded...
2018/0197860 FinFET CMOS WITH SILICON FIN N-CHANNEL FET AND SILICON GERMANIUM FIN P-CHANNEL FET
A substrate having a silicon region and a silicon germanium region is provided. A first set of fins in the silicon region and a second set of fins in the...
2018/0197859 SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third...
2018/0197858 STRUCTURE AND METHOD FOR EQUAL SUBSTRATE TO CHANNEL HEIGHT BETWEEN N AND P FIN-FETS
A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two...
2018/0197857 FinFET Transistor with Fin Back Biasing
A semiconductor device includes multiple first fins oriented lengthwise along a first direction and multiple first gate structures oriented lengthwise along a...
2018/0197856 Semiconductor Device Containing HEMT and MISFET and Method of Forming the Same
A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V...
2018/0197855 COMPOSITE SEMICONDUCTOR DEVICE
A composite semiconductor device with improved response performance and reliability is provided while an increase in wiring area being suppressed. Fingers 1...
2018/0197854 POWER SEMICONDUCTOR DEVICE HAVING TRENCH GATE TYPE IGBT AND DIODE REGIONS
Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region....
2018/0197853 POWER SEMICONDUCTOR DEVICE HAVING TRENCH GATE TYPE IGBT AND DIODE REGIONS
Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region....
2018/0197852 Method of Producing a Semiconductor Device
A semiconductor body having a drift region layer, a body region layer adjoining the drift region layer, and a source region layer adjoining the body region...
2018/0197851 CASCODE CIRCUIT HAVING A GATE OF A LOW-SIDE TRANSISTOR COUPLED TO A HIGH-SIDE TRANSISTOR
In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the...
2018/0197850 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A semiconductor integrated circuit device with a "PAD on I/O cell" structure in which a pad lead part is disposed almost in the center of an I/O part so as to...
2018/0197849 DISPLAY DEVICE
An organic light emitting display device comprising a display panel including an active area where an image is displayed and a pad area corresponding to a...
2018/0197848 DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES WITH A DISTRIBUTED TRIGGER CIRCUIT
An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a...
2018/0197847 Package-on-Package Structures and Methods for Forming the Same
A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further...
2018/0197846 Packaging Mechanisms for Dies With Different Sizes of Connectors
A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. A bottommost surface of the redistribution...
2018/0197845 MAGNETIC SMALL FOOTPRINT INDUCTOR ARRAY MODULE FOR ON-PACKAGE VOLTAGE REGULATOR
An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements...
2018/0197844 LIGHT EMITTING STRUCTURE
A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a...
2018/0197843 OPTOELECTRONIC SEMICONDUCTOR COMPONENT
An optoelectronic semiconductor component is disclosed, comprising: a semiconductor body (1) having a semiconductor layer sequence (2) with a p-type...
2018/0197842 OPTOELECTRONIC CHIP EMBEDDED ORGANIC SUBSTRATE
Optoelectronic devices and method of forming the same include an optoelectronic chip in a substrate layer, the optoelectronic chip having one or more...
2018/0197841 LIGHTING MODULE
The invention relates to a lighting module (1) comprising an assembly body (3) extending between a rear side (31) and a front side (30) opposite the rear side,...
2018/0197840 INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first...
2018/0197839 Packages with Metal Line Crack Prevention Design
A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to...
2018/0197838 POWER SEMICONDUCTOR DEVICE
Provided is a power semiconductor device which is able to have improved connection reliability between a wiring line and an electrode of a power semiconductor...
2018/0197837 Integrated Fan-out Package and the Methods of Manufacturing
A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad...
2018/0197836 CLIP AND RELATED METHODS
Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section...
2018/0197835 A SURFACE MOUNT DEVICE AND A METHOD OF ATTACHING SUCH A DEVICE
A device comprises a surface mount component on a substrate, in which the surface mount component is attached by a set of discrete mechanical coupling parts...
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