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Patent # Description
2018/0197834 Wire Bonding Method and Apparatus for Electromagnetic Interference Shielding
Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a...
2018/0197833 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
The manufacturing method of a semiconductor device includes applying a conductive paste containing metal particles to a specified area in an electrode plate...
2018/0197832 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
2018/0197831 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked...
2018/0197830 INTEGRATED CIRCUIT WAVE DEVICE AND METHOD
In described examples of forming an integrated circuit wave device, a method includes: (a) affixing an integrated circuit die relative to a substrate; (b)...
2018/0197829 THREE-DIMENSIONAL INTEGRATED CIRCUIT ASSEMBLY WITH ACTIVE INTERPOSER
Embodiments of the disclosure relate to a three-dimensional (3D) integrated circuit (IC) (3DIC) assembly with active interposer. The 3DIC assembly includes an...
2018/0197828 VANISHING VIA FOR HARDWARE IP PROTECTION FROM REVERSE ENGINEERING
A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an...
2018/0197827 FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME
The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a...
2018/0197826 THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) WITH SUPPORT STRUCTURES
Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor...
2018/0197825 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER
A semiconductor wafer provided with a pseudo chip between a product chip and a pattern prohibiting region is prepared. With the edge portion of the...
2018/0197824 ANTI-EMI SHIELDING PACKAGE AND METHOD OF MAKING SAME
A method of manufacturing anti-EMI shielding package includes manufacturing a substrate having a grounding terminal and a first through hole with a conductive...
2018/0197823 SEMICONDUCTOR DEVICE CHIP AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CHIP
A semiconductor device chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a semiconductor...
2018/0197822 Semiconductor Device and Semiconductor Device Manufacturing Method
A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a...
2018/0197821 Semiconductor Package With EMI Shield and Fabricating Method Thereof
A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all...
2018/0197820 MARK, METHOD FOR FORMING SAME, AND EXPOSURE APPARATUS
A mark forming method includes: forming recessed portion on a mark formation area of a substrate; coating the recessed portion with a polymer layer containing...
2018/0197819 INTERCONNECT STRUCTURE AND FABRICATING METHOD THEREOF
An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is...
2018/0197818 WIRING BOARD WITH EMBEDDED COMPONENT AND INTEGRATED STIFFENER, METHOD OF MAKING THE SAME AND FACE-TO-FACE...
A wiring board includes an electronic component laterally surrounded by a stiffener, and a third routing circuitry disposed beyond the space laterally...
2018/0197817 SEMICONDUCTOR DEVICE INCLUDING FUSE STRUCTURE
An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between...
2018/0197816 IMPROVED TRANSFORMER FOR A CIRCUIT IN MMIC TECHNOLOGY
This transformer includes primary and secondary tracks (10, 20) that are coupled to one another by mutual inductance, the primary and secondary tracks being...
2018/0197815 INTERCONNECTION STRUCTURES FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
An interconnection structure includes an underlying layer including a lower interconnection, and an interlayered dielectric layer including a contact hole and...
2018/0197814 ELECTRONIC CIRCUIT AND CAMERA
An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for...
2018/0197813 SEMICONDUCTOR DEVICE
An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device...
2018/0197812 3D SEMICONDUCTOR DEVICE AND STRUCTURE
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the...
2018/0197811 Molding Compound Structure
A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the...
2018/0197810 LEAD FRAME AND METHOD OF MANUFACTURING THE SAME
A lead frame includes leads including inner leads and outer leads. Each of the leads includes an inner lead and an outer lead. A tie bar extends so as to cross...
2018/0197809 SEMICONDUCTOR DEVICE WITH FRAME HAVING ARMS AND RELATED METHODS
A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending...
2018/0197808 CONDUCTIVE CLIP CONNECTION ARRANGEMENTS FOR SEMICONDUCTOR PACKAGES
Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements...
2018/0197807 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element, a lead on which the semiconductor element is mounted, a bonding member fixing the semiconductor...
2018/0197806 COOLING DEVICE, METHOD FOR PRODUCING A COOLING DEVICE AND POWER CIRCUIT
A cooling device includes an aluminum heat sink and at least one nickel sheet segment. The nickel sheet segment is connected to the aluminum heat sink by a...
2018/0197805 SURFACE PASSIVATION HAVING REDUCED INTERFACE DEFECT DENSITY
Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect...
2018/0197804 SURFACE PASSIVATION HAVING REDUCED INTERFACE DEFECT DENSITY
Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect...
2018/0197803 THERMALLY ENHANCED SEMICONDUCTOR PACKAGE WITH THERMAL ADDITIVE AND PROCESS FOR MAKING THE SAME
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a...
2018/0197802 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element, a base, and an outer packaging resin. The base has a mounting surface, on which the semiconductor...
2018/0197801 SEMICONDUCTOR DEVICE, CHIP MODULE, AND SEMICONDUCTOR MODULE
Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main...
2018/0197800 AIR-CAVITY PACKAGE WITH DUAL SIGNAL-TRANSITION SIDES
The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component,...
2018/0197799 SEMICONDUCTOR MODULE
A semiconductor module includes a case. The case includes a bottom part, a case frame, and a case lid. An inner electrode and a stud bolt are provided inside...
2018/0197797 ENDPOINT BOOSTER SYSTEMS
An endpoint booster transports an optical signal from inside of a plasma etch chamber through a viewport to an optical cable outside of the plasma etch...
2018/0197796 CRITICAL DIMENSIONS VARIANCE COMPENSATION
An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer...
2018/0197795 Replacement Gate Process for Semiconductor Devices
Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate,...
2018/0197794 FABRICATING METHOD OF NANOSHEET TRANSISTOR SPACER INCLUDING INNER SPACER
A fabricating method of a nanosheet transistor includes: forming a plurality of sacrificial layers and a plurality of channel layers on a substrate, wherein...
2018/0197793 SELF-ALIGNED DOPING IN SOURCE/DRAIN REGIONS FOR LOW CONTACT RESISTANCE
Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method...
2018/0197792 SELF-ALIGNED DOPING IN SOURCE/DRAIN REGIONS FOR LOW CONTACT RESISTANCE
Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method...
2018/0197791 Semiconductor Devices Having FIN Active Regions
Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate...
2018/0197790 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor is provided. A first oxide layer is formed on a substrate. A first nitride layer is formed on the first oxide layer....
2018/0197789 REPLACEMENT CHANNEL ETCH FOR HIGH QUALITY INTERFACE
Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and...
2018/0197788 3D VERTICAL FET WITH TOP AND BOTTOM GATE CONTACTS
A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side...
2018/0197787 3D VERTICAL FET WITH TOP AND BOTTOM GATE CONTACTS
A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side...
2018/0197786 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an...
2018/0197785 NANOSHEET TRANSISTORS HAVING DIFFERENT GATE DIELECTRIC THICKNESSES ON THE SAME CHIP
Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first...
2018/0197784 NANOSHEET TRANSISTORS HAVING DIFFERENT GATE DIELECTRIC THICKNESSES ON THE SAME CHIP
Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first...
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