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Patent # Description
2018/0197783 Method of Forming a Fin Structure of Semiconductor Device
A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are...
2018/0197782 Fin Spacer Protected Source and Drain Regions in FinFETs
A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method...
2018/0197781 PNP-TYPE BIPOLAR TRANSISTOR MANUFACTURING METHOD
A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type...
2018/0197780 FIELD EFFECT TRANSISTOR INCLUDING STRAINED GERMANIUM FINS
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region...
2018/0197779 Organic Light Emitting Diode Display Device and Method of Fabricating the Same
An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed...
2018/0197778 MEMORY AND FABRICATION METHOD THEREOF
A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first...
2018/0197777 MANUFACTURING PROCESS OF ELEMENT CHIP
Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having...
2018/0197776 RESIN PACKAGE SUBSTRATE PROCESSING METHOD
Disclosed herein is a resin package substrate processing method for processing a resin package substrate including a mold resin in which a filler is mixed. The...
2018/0197775 SEMICONDUCTOR DEVICE WITH AN INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME
A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure...
2018/0197774 COBALT CONTACT AND INTERCONNECT STRUCTURES
Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to...
2018/0197773 COBALT CONTACT AND INTERCONNECT STRUCTURES
Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to...
2018/0197772 HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM
A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may...
2018/0197771 METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH INTERCONNECT STRUCTURE
A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The...
2018/0197770 DEPOSITION OF ALUMINUM OXIDE ETCH STOP LAYERS
Aluminum oxide films characterized by a dielectric constant (k) of less than about 7 (such as between about 4-6) and having a density of at least about 2.5...
2018/0197769 SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A SACRIFICIAL LAYER AND METHOD OF MANUFACTURE THEREOF
A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.
2018/0197768 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a...
2018/0197767 TRANSFER APPARATUS AND TRANSFER METHOD
A transfer apparatus and a transfer method are provided. The transfer apparatus includes a transfer substrate; and a plurality of gripping members arranged in...
2018/0197766 Wafer Carrier, Method for Manufacturing the Same and Method for Carrying a Wafer
A wafer carrier comprises a first foil, a second foil, and a chamber between the first and the second foil. The first foil has a perforation and is used for...
2018/0197765 WAFER PROCESSING METHOD AND ADHESIVE TAPE
Disclosed is a wafer processing method for dividing a wafer into individual chips by applying to the wafer a laser beam having such a wavelength as to be...
2018/0197764 SEMICONDUCTOR WAFER SURFACE PROTECTION FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor wafer surface protection film has a substrate layer A, an adhesive absorption layer B, and adhesive surface layer C, in the stated order....
2018/0197763 Substrate Alignment Detection Using Circumferentially Extending Timing Pattern
Apparatus and method for aligning a rotatable substrate to a support mechanism to write a feature to the substrate, and a substrate so configured. In some...
2018/0197762 Apparatus and Methods for Testing Semiconductor Devices
The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and...
2018/0197761 ACTIVE WORKPIECE HEATING OR COOLING FOR AN ION IMPLANTATION SYSTEM
A heated chuck for an ion implantation system selectively clamps a workpiece to a carrier plate having heaters to selectively heat a clamping surface. A gap...
2018/0197760 Dual PVD Chamber And Hybrid PVD-CVD Chambers
Processing platforms comprising a central transfer station having at least one robot and a dual chamber processing chamber connected to a side of the central...
2018/0197759 HEAT TREATMENT APPARATUS AND TEMPERATURE CONTROL METHOD
Disclosed is a heat treatment apparatus including: a processing container configured to accommodate a substrate; a furnace body having a heater configured to...
2018/0197758 ELECTROSTATIC PUCK ASSEMBLY WITH METAL BONDED BACKING PLATE FOR HIGH TEMPERATURE PROCESSES
An electrostatic puck assembly includes an upper puck plate, a lower puck plate and a backing plate. The upper puck plate comprises AlN or Al.sub.2O.sub.3 and...
2018/0197757 METHOD OF MANUFACTURING A HIGH DEFINITION HEATER SYSTEM
A method of manufacturing a heater includes forming a first laminate having a first double-sided adhesive dielectric layer, a sacrificial layer, and a...
2018/0197756 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
According to the present invention, after supplying a rinse liquid containing water to a substrate that is held horizontally, an IPA-containing liquid which...
2018/0197755 Integrated Passive Device Package and Methods of Forming Same
An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The...
2018/0197754 INTEGRATED CIRCUIT PACKAGE
The present invention relates to an integrated circuit packaging, comprising: a plurality of electrical circuits using a first patterned conductive layer (103)...
2018/0197753 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a...
2018/0197752 TUNABLE TiOxNy HARDMASK FOR MULTILAYER PATTERNING
Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic...
2018/0197751 EPITAXIAL SILICON WAFER
An epitaxial silicon wafer includes a silicon wafer consisting of a COP region in which a nitrogen concentration is 1.times.10.sup.8-3.times.10.sup.9...
2018/0197750 Via Connection to a Partially Filled Trench
An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric...
2018/0197749 PLANARIZATION METHOD
A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the...
2018/0197748 SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS
In a substrate processing method for performing predetermined processing on a substrate, which has a processing target film, accommodated in a processing...
2018/0197747 TECHNIQUES FOR FORMING ISOLATION STRUCTURES IN A SUBSTRATE
A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality...
2018/0197746 FORMULATIONS TO SELECTIVELY ETCH SILICON GERMANIUM RELATIVE TO GERMANIUM
Compositions useful for the selective removal of silicon germanium materials relative to germanium-containing materials and silicon-containing materials from a...
2018/0197745 HARD MASKS FOR BLOCK PATTERNING
Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block...
2018/0197744 HARD MASKS FOR BLOCK PATTERNING
Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block...
2018/0197743 LAYOUT EFFECT MITIGATION IN FINFET
Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor...
2018/0197742 DOPING METHOD FOR SEMICONDUCTOR DEVICE
A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel...
2018/0197741 METHOD FOR PREPARING SUBSTRATE WITH INSULATED BURIED LAYER
A method for preparing a substrate with an insulating buried layer includes: providing a substrate, the substrate having a supporting layer and an insulating...
2018/0197740 METHODS OF FABRICATING SEMICONDUCTOR DEVICE
An etching target layer is formed on a substrate. An upper mask layer is formed on the etching target layer. A plurality of preliminary mask patterns is formed...
2018/0197739 FIN PATTERNS WITH VARYING SPACING WITHOUT FIN CUT
Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of multiple mandrels using an angled deposition process. A...
2018/0197738 SELF ALIGNED PATTERN FORMATION POST SPACER ETCHBACK IN TIGHT PITCH CONFIGURATIONS
A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming...
2018/0197737 HIGH ELECTRON MOBILITY TRANSISTOR MANUFACTURING METHOD AND HIGH ELECTRON MOBILITY TRANSISTOR
Examples of a high electron mobility transistor manufacturing method includes forming a buffer layer including a nitride semiconductor doped with any one of...
2018/0197736 SYSTEMS AND METHODS FOR GRAPHENE BASED LAYER TRANSFER
A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor,...
2018/0197735 SILICON CHALCOGENATE PRECURSORS AND METHODS OF FORMING THE SILICON CHALCOGENATE PRECURSORS
A silicon chalcogenate precursor comprising the chemical formula of Si(XR.sup.1).sub.nR.sup.2.sub.4-n, where X is sulfur, selenium, or tellurium, R.sup.1 is...
2018/0197734 BUFFER LAYER TO INHIBIT WORMHOLES IN SEMICONDUCTOR FABRICATION
Reducing wormhole formation during n-type transistor fabrication includes providing a starting structure, the starting structure including a semiconductor...
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