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Patent # Description
2018/0196776 DATA BUS ACTIVATION IN AN ELECTRONIC DEVICE
Data bus activation in an electronic device is provided. In one aspect, a host circuit determines a cumulative potential representing a cumulative fractional...
2018/0196775 EXTREMELY HIGH FREQUENCY SYSTEMS AND METHODS OF OPERATING THE SAME TO ESTABLISH USB DATA TRANSPORT PROTOCOLS
EHF communication systems described herein can selectively implement any one of the USB standards by mapping appropriate USB signal conditions over an EHF...
2018/0196774 CONTROL MESSAGING IN MULTISLOT LINK LAYER FLIT
A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are...
2018/0196773 METHOD AND HOST NODE FOR CONFIGURING A REMOTE NODE AND A HOST NODE
Embodiments of the present technology presented herein relate to a method for configuring a remote node and to a host node for performing said configuring of...
2018/0196772 Uma-Aware Root Bus Selection
A method includes determining a first host Non-Uniform Memory Access (NUMA) node of a plurality of host NUMA nodes on a host machine that provides a virtual...
2018/0196771 CENTRAL ARBITRATION SCHEME FOR A HIGHLY EFFICIENT INTERCONNECTION TOPOLOGY IN A GPU
According to one general aspect, an apparatus may include a network of node circuits and a central arbiter circuit. The network of node circuits is within an...
2018/0196770 FORCED COMPRESSION OF SINGLE I2C WRITES
Systems, methods, and apparatus are described that enable a physical layer interface of a device coupled to a serial bus to combine two or more single-byte...
2018/0196769 CIRCUITRY
A circuitry includes a source circuit; a first circuit; a second circuit; and a data-distributing circuit including: a receiving circuit configured to receive...
2018/0196768 SEMICONDUCTOR MEMORY DEVICE WITH DATA BUFFERING
A semiconductor storage device includes at least two nonvolatile semiconductor memories, a buffer in which data received from a host and to be written to the...
2018/0196767 Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices
A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the...
2018/0196766 Memory Controller, Memory Control Method and Semiconductor Storage Apparatus
In a memory controller, command, address and data are allocated to transmit the command, the address and the data to each of the plurality of memory devices...
2018/0196765 Column Bus Driving Method For Micro Display Device
A method of generating column signals for use by a pixel array includes connecting two or more controllable bus buffers in series. The output of each of the...
2018/0196764 COMPUTING MODULE WITH SERIAL DATA CONNECTIVITY
A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that...
2018/0196763 FLEXIBLE HIGH-DENSITY MEMORY MODULE
A flexible high-density memory module for use with an electronic computing device includes an interposer and a controller supported on a first substrate, a...
2018/0196762 CONTENT SEARCH EXTENSION ARCHITECTURE FOR PROGRAMMABLE INTELLIGENT SEARCH MEMORY
An integrated circuit chip is disclosed that comprises a programmable intelligent search memory (PRISM) for content search.
2018/0196761 METHOD FOR SECURELY AND EFFICIENTLY ACCESSING CONNECTION DATA
A method is provided for securely and efficiently accessing connection data of at least one telecommunication provider is provided, wherein the connection data...
2018/0196760 METHOD AND APPARATUS FOR SUGGESTING DATA FOR DELETION
An approach is provided for suggesting data for deletion from an electronic data storage medium. An external device detects initiation of transfer of data from...
2018/0196759 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
2018/0196758 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
2018/0196757 VIRTUAL ADDRESS TABLE
The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that...
2018/0196756 ADDRESS MAPPING METHOD OF MEMORY SYSTEM
Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a...
2018/0196755 STORAGE APPARATUS, RECORDING MEDIUM, AND STORAGE CONTROL METHOD
To prevent an excessive increase of a dirty data amount in a cache memory. A processor acquires storage device information from each of storage devices. When...
2018/0196754 TEMPORARILY SUPPRESSING PROCESSING OF A RESTRAINED STORAGE OPERAND REQUEST
Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage...
2018/0196753 PRE-FETCHING DATA FROM BUCKETS IN REMOTE STORAGE FOR A CACHE
Embodiments are disclosed for a prefetching method that may include copying, in response to a search query, a first bucket from a remote storage to a cache....
2018/0196752 HYBRID MAIN MEMORY USING A FINE-GRAIN LEVEL OF REMAPPING
Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory...
2018/0196751 FACILITY FOR EXTENDING EXCLUSIVE HOLD OF A CACHE LINE IN PRIVATE CACHE
A computing environment facility is provided to extend a hold of a cache line in private (or local) cache exclusively after processing a storage operand...
2018/0196750 AGGREGATING MESSAGES FOR REDUCING CACHE INVALIDATION RATE
A storage device includes a nonvolatile memory and a controller. The controller is configured to store in the nonvolatile memory data for a host, to generate...
2018/0196749 MEMORY SYSTEM AND OPERATING METHOD OF THE SAME
An memory system includes a memory device that includes a first memory block and a super memory block including simultaneously controllable second memory...
2018/0196748 PAGE CACHE IN A NON-VOLATILE MEMORY
A system includes a non-volatile memory to store a page cache that contains pages of data allocated by an operating system, the pages in the page cache being...
2018/0196747 DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD
A mapping information rebuilding technique for a flash memory is introduced. Mapping information of data that has been stored in the flash memory is recorded...
2018/0196746 APPARATUS AND METHOD FOR EXECUTING INSTRUCTION USING RANGE INFORMATION ASSOCIATED WITH A POINTER
An apparatus (2) comprises one or more bounded pointer storage element (60s) each to store a pointer (62) having associated range information (64) indicating...
2018/0196745 GARBAGE COLLECTION OF DATA BLOCKS IN A STORAGE SYSTEM WITH DIRECT-MAPPED STORAGE DEVICES
An indication to perform a garbage collection process for multiple erase blocks at a storage array that includes multiple storage devices may be received....
2018/0196744 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks and a controller. The controller manages a garbage...
2018/0196743 DIRECTED SANITIZATION OF MEMORY
The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a...
2018/0196742 SYSTEM AND METHOD FOR END TO END PERFORMANCE RESPONSE TIME MEASUREMENT BASED ON GRAPHIC RECOGNITION
Software testing techniques based on image recognition are disclosed. In various embodiments, a programmatically implemented image classifier is trained to...
2018/0196741 USING CONTAINERS FOR UPDATE DEPLOYMENT
A system and method for software deployment, where the system and method include, at a deployment service, obtaining a software package and determining that a...
2018/0196740 AUTOMATIC RISK ANALYSIS OF SOFTWARE
Techniques are described herein that are capable of performing automatic risk analysis of software. An automatic risk analyzer may determine correlations...
2018/0196739 SYSTEM AND METHOD FOR SAFETY-CRITICAL SOFTWARE AUTOMATED REQUIREMENTS-BASED TEST CASE GENERATION
Automated requirements-based test case generation method includes constructing a software architecture model derived from software design model architectural...
2018/0196738 TEST INPUT INFORMATION SEARCH DEVICE AND METHOD
A test input information search device searches for a candidate for test inputting in a database, and stores information of the database including a plurality...
2018/0196737 BIFURCATING A MULTILAYERED COMPUTER PROGRAM PRODUCT
Technical solutions are described for debugging a computer program product. An example computer-implemented method includes receiving an identifier of a...
2018/0196736 CONTROLLING DEBUG PROCESSING
Execution of a debug process on a thread of an application is monitored to detect resource contention caused by the debug process. In response to detecting a...
2018/0196735 AUTOMATIC INSTRUMENTATION OF CODE
A code repository receives and analyzes changed code to determine whether and how to automatically instrument the code. The code repository identifies...
2018/0196734 PRE-FETCHING DISASSEMBLY CODE FOR REMOTE SOFTWARE DEBUGGING
A method, computer program product and/or system for pre-fetching disassembly code. A breakpoint is set within an application under test (AUT). Setting of the...
2018/0196733 PRE-FETCHING DISASSEMBLY CODE FOR REMOTE SOFTWARE DEBUGGING
A method, computer program product and/or system for pre-fetching disassembly code. A breakpoint is set within an application under test (AUT). Setting of the...
2018/0196732 METHOD AND SYSTEM FOR TESTING AND CHECKING THE CORRECTNESS OF A COMPUTER PROGRAM DURING RUNTIME
The present invention is directed to a method and system for testing, during runtime, the correctness of a computer program (such as a hypervisor, an operating...
2018/0196731 SYSTEM FOR DISTRIBUTED SOFTWARE QUALITY IMPROVEMENT
Provided is a system for building and validating an application (including e.g., various software versions and revisions, programming languages, code segments,...
2018/0196730 DEBUG MANAGEMENT IN A DISTRIBUTED BATCH DATA PROCESSING ENVIRONMENT
Disclosed aspects relate to debug management in a distributed batch data processing environment which uses a shared pool of configurable computing resources. A...
2018/0196729 PATTERN ORIENTED DATA COLLECTION AND ANALYSIS
A process for determining a problematic condition while running software includes: loading a first pattern data set into a volatile memory of a computer, with...
2018/0196728 METHOD FOR DEBUGGING SOFTWARE COMPONENTS IN A DISTRIBUTED, TIME-CONTROLLED REAL TIME SYSTEM
The invention relates to a method for debugging software components of a distributed real-time software system, wherein the target hardware comprises computer...
2018/0196727 TIME-SLICE-INSTRUMENTATION FACILITY
A facility is provided for collecting time-slice-instrumentation information during processing unit execution. The facility counts, at least in part,...
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