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Patent # Description
2018/0204967 Segmented Solar Module
A segmented solar module is disclosed. One or more Photovoltaic (PV) submodules are connected together with embedded parallel wiring that facilitates the...
2018/0204966 SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SAME
A solar cell module includes: a first cover in the form of a plate having at least a portion transparently; a second cover disposed to face the first cover; at...
2018/0204965 SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME, AND SOLAR CELL MODULE
A solar cell module includes a plurality of solar cells comprising a first solar cell and a second solar cell adjacent to each other, a conductive ribbon...
2018/0204964 SOLAR CELL AND SOLAR CELL PANEL INCLUDING THE SAME
A solar cell includes a semiconductor substrate, an emitter formed on a first surface of the semiconductor substrate, a back surface field formed on a second...
2018/0204963 Pre-Equilibrium System and Method Using Solid-State Devices as Energy Converters Using Nano-Engineered Porous...
An energy conversion device for conversion of various energy forms into electricity. The energy forms may be chemical, photovoltaic or thermal gradients. The...
2018/0204962 SOLAR CELL
Disclosed is a solar cell including: a semiconductor substrate; a conductive region on or at the semiconductor substrate; an electrode electrically connected...
2018/0204961 IMAGE SENSOR HAVING LIGHT REFRACTIVE PATTERNS
An image sensor is provided. The image sensor may include a photodiode formed in a substrate; a light refraction pattern formed on the photodiode; a color...
2018/0204960 EPITAXIAL SILICON WAFER
An epitaxial silicon wafer is provided with a boron-doped silicon substrate and an epitaxial layer formed on a surface of the silicon substrate, wherein the...
2018/0204959 OPTOELECTRONIC MODULES AND METHODS FOR MANUFACTURING THE SAME
Optoelectronic modules, such as imaging cameras, proximity sensors, range cameras, structured-light/pattern generators, and image projectors, and methods for...
2018/0204958 SEMICONDUCTOR STRUCTURE
A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating...
2018/0204957 METHOD OF MANUFACTURING THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR
A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer...
2018/0204956 Field-Effect Transistors Having Black Phosphorus Channel and Methods of Making the Same
Various transistors, such as field-effect transistors, and methods of fabricating the transistors are disclosed herein. An exemplary transistor includes a...
2018/0204955 SEMICONDUCTOR NANOWIRE DEVICE HAVING CAVITY SPACER AND METHOD OF FABRICATING CAVITY SPACER FOR SEMICONDUCTOR...
Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a...
2018/0204954 TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
A transistor array panel according to an exemplary embodiment includes a substrate, and a first transistor and a second transistor positioned on the substrate....
2018/0204952 OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME
The present disclosure relates to an oxide thin film transistor and a fabricating method thereof. In the oxide thin film transistor, which uses amorphous zinc...
2018/0204951 VERTICAL TRANSISTORS WITH IMPROVED TOP SOURCE/DRAIN JUNCTIONS
A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel...
2018/0204950 VERTICAL TRANSISTORS WITH IMPROVED TOP SOURCE/DRAIN JUNCTIONS
A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel...
2018/0204949 THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY PANEL
A thin film transistor and a fabrication method thereof, an array substrate, and a display panel are provided. The fabrication method of the thin film...
2018/0204948 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided....
2018/0204947 A TRANSISTOR WITH A SUBFIN LAYER
A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing...
2018/0204946 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate, and a first source/drain region formed on the substrate. The semiconductor device further includes a channel...
2018/0204945 VERTICAL FET STRUCTURE
A vertical FET includes a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom...
2018/0204944 SEMICONDUCTOR DEVICE STRUCTURE
The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a...
2018/0204943 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is...
2018/0204942 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon...
2018/0204941 GALLIUM NITRIDE EPITAXIAL STRUCTURES FOR POWER DEVICES
A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the...
2018/0204940 GROUP III - NITRIDE DOUBLE-HETEROJUNCTION FIELD EFFECT TRANSISTOR
A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on...
2018/0204939 SEMICONDUCTOR DEVICE INCLUDING QUANTUM WIRES
A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a...
2018/0204938 INSULATED GATE BIPOLAR TRANSISTOR AND FABRICATION METHOD THEREOF
An insulated gate bipolar transistor and a method for fabricating the insulated gate bipolar transistor are provided. The insulated gate bipolar transistor...
2018/0204937 METHODS FOR FABRICATING ANODE SHORTED FIELD STOP INSULATED GATE BIPOLAR TRANSISTOR
A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor...
2018/0204936 SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first...
2018/0204935 SEMICONDUCTOR MODULE
In a semiconductor device according to an embodiment, ends of conductor portions are electrically connected to an overvoltage protection diode so that...
2018/0204934 METHODS RELATED TO A SEMICONDUCTOR STRUCTURE WITH GALLIUM ARSENIDE AND TANTALUM NITRIDE
Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be...
2018/0204933 SOI FINFET TRANSISTOR WITH STRAINED CHANNEL
Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency...
2018/0204932 VERTICAL INTEGRATION SCHEME AND CIRCUIT ELEMENTS ARCHITECTURE FOR AREA SCALING OF SEMICONDUCTOR DEVICES
Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure...
2018/0204931 METHOD FOR FABRICATING A TRANSISTOR HAVING A VERTICAL CHANNEL HAVING NANO LAYERS
The invention relates to a process for fabricating a vertical transistor, comprising the step of providing a substrate surmounted by a stack of first, second...
2018/0204930 3D INTEGRATED CIRCUIT DEVICE
A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first...
2018/0204929 METAL GATE FORMATION USING AN ENERGY REMOVAL FILM
Structures for a field-effect transistor and methods for forming a field-effect transistor. An interlayer dielectric layer is formed on a substrate. An energy...
2018/0204928 NITRIDE SEMICONDUCTOR DEVICE AND PROCESS OF FORMING THE SAME
A process of forming a HEMT that makes the contract resistance of a non-rectifying electrode consistent with other device performance is disclosed. The process...
2018/0204927 AIR-GAP GATE SIDEWALL SPACER AND METHOD
Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall...
2018/0204926 TRANSISTOR USING SELECTIVE UNDERCUT AT GATE CONDUCTOR AND GATE INSULATOR CORNER
Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator...
2018/0204925 FIELD EFFECT TRANSISTOR WHICH CAN BE BIASED TO ACHIEVE A UNIFORM DEPLETION REGION
A Field Effect Transistor includes a channel with one end designated the source and the other end designated the drain. The Field Effect Transistor also...
2018/0204924 SEMICONDUCTOR DEVICE HAVING MULTIPLE WELLS
A semiconductor device includes a substrate and a gate structure over a top surface of the substrate. The semiconductor device further includes a source in the...
2018/0204923 METHOD AND STRUCTURE FOR A LARGE-GRAIN HIGH-K DIELECTRIC
A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first...
2018/0204922 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An...
2018/0204921 FULLY DEPLETED SOI DEVICE FOR REDUCING PARASITIC BACK GATE CAPACITANCE
A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin...
2018/0204920 FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD
Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to...
2018/0204919 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one...
2018/0204918 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a drain region formed on a rear surface side of a substrate; a base layer formed between the drain region and a front surface...
2018/0204917 Power MOSFET with a Deep Source Contact
A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of...
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