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Patent # Description
2018/0204866 SEMICONDUCTOR DIE AND METHOD OF PACKAGING MULTI-DIE WITH IMAGE SENSOR
A semiconductor wafer has an image sensor area with a light transmissive wafer, such as glass, disposed over the semiconductor wafer. A portion of the...
2018/0204865 PHOTOELECTRIC CONVERSION ELEMENT, IMAGE PICKUP ELEMENT, LAMINATED IMAGE PICKUP ELEMENT, AND IMAGE PICKUP DEVICE
In an image pickup element or a photoelectric conversion element, at least an anode 21, a carrier blocking layer 22, an organic photoelectric conversion layer...
2018/0204864 METAL MIRROR BASED MULTISPECTRAL FILTER ARRAY
A device may include a multispectral filter array disposed on the substrate. The multi spectral filter array may include a first metal mirror disposed on the...
2018/0204863 IMAGE SENSOR, AN IMAGING DEVICE, AN IMAGING SYSTEM AND A METHOD FOR SPECTRAL IMAGING
The present invention relates to an image sensor for spectral imaging, said image sensor comprising: an array of light-detecting elements; and at least one...
2018/0204862 EXTRA DOPED REGION FOR BACK-SIDE DEEP TRENCH ISOLATION
The present disclosure, in some embodiments, relates to a CMOS image sensor. The CMOS image sensor has an image sensing element disposed within a substrate. A...
2018/0204861 METHODS AND APPARATUS FOR AN IMAGE SENSOR
Various embodiments of the present technology may comprise a method and apparatus for an image sensor. The image sensor may comprise a color filter with a...
2018/0204860 LIGHT-RECEIVING DEVICE AND PHOTO-DETECTION APPARATUS WITH SUCH LIGHT-RECEIVING DEVICE
A light-receiving device has a semiconductor substrate that includes a first pixel region that has a first thickness and a second pixel region that has a...
2018/0204859 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE AND MASK PLATE
A method for manufacturing an array substrate includes (S1) forming a pattern including a gate electrode and a gate line, (S2) forming an insulating layer,...
2018/0204858 DISPLAY SUBSTRATE HAVING AN ORGANIC LAYER AND FABRICATING METHOD THEREOF
The present application discloses a method of fabricating a display substrate having an organic layer for reducing parasitic capacitance between electrodes in...
2018/0204857 ELECTRICAL CONNECTION STRUCTURE AND THIN FILM TRANSISTOR ARRAY SUBSTRATE INCLUDING ELECTRICAL CONNECTION STRUCTURE
An electrical connection structure providing better optical properties in a display includes an electrical connection unit, an interference layer, and an...
2018/0204856 TRANSISTOR ARRAY PANEL
A transistor display panel includes a substrate, a gate line disposed on the substrate, a data line disposed on the substrate, and a transistor disposed on the...
2018/0204855 LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the...
2018/0204854 DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE
The disclosure discloses a display substrate and a manufacturing method thereof, and a display device, the display substrate comprises a display region and a...
2018/0204853 ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME, AND IN-CELL TOUCH PANEL-TYPE DISPLAY DEVICE
An active matrix substrate (1001) includes a connecting portion (101). The connecting portion. (101) includes a lower conductive layer supported by a...
2018/0204852 MANUFACTURING METHODS OF ARRAY SUBSTRATES AND ARRAY SUBSTRATES
The present disclosure relates to an array substrate and the manufacturing method thereof. The manufacturing method includes the steps including: forming a...
2018/0204851 Memory Arrays and Methods of Fabricating Integrated Structures
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and...
2018/0204850 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell...
2018/0204849 Memory Cells, Integrated Structures and Memory Arrays
Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a...
2018/0204848 SEMICONDUCTOR MEMORY CELL STRUCTURE
A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the...
2018/0204847 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
The reliability of a semiconductor device is improved. A control gate electrode and a memory gate electrode for memory cell of a nonvolatile memory, a first...
2018/0204846 MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least...
2018/0204845 Three-Dimensional Vertical Multiple-Time-Programmable Memory Comprising Multiple Re-programmable Sub-Layers
The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTP.sub.V). It comprises horizontal address lines and memory...
2018/0204844 Three-Dimensional Vertical One-Time-Programmable Memory Comprising Multiple Antifuse Sub-Layers
The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTP.sub.V). It comprises horizontal address lines and memory...
2018/0204843 SEMICONDUCTOR MEMORY DEVICES
A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a...
2018/0204842 A STACKABLE THIN FILM MEMORY
A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a...
2018/0204841 SEMICONDUCTOR DEVICE
An HVNMOS having a source follower configuration is disposed in an n.sup.- diffusion region that forms an HVJT. The lateral HVNMOS includes a p-type back gate...
2018/0204840 SELF-ALIGNED JUNCTION STRUCTURES
The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The...
2018/0204839 FORMATION OF FULL METAL GATE TO SUPPRESS INTERFICIAL LAYER GROWTH
A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom...
2018/0204838 INTEGRATED CIRCUIT STRUCTURE WITH SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAME
An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within...
2018/0204837 MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in...
2018/0204836 Metal Gate Isolation Structure and Method Forming Same
A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region...
2018/0204835 SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a...
2018/0204834 APPROACH TO FABRICATION OF AN ON-CHIP RESISTOR WITH A FIELD EFFECT TRANSISTOR
A method of forming a resistor adjacent to a fin field effect transistor on a substrate, including, forming a plurality of vertical fins on the substrate,...
2018/0204833 FORMING VERTICAL TRANSISTORS AND METAL-INSULATOR-METAL CAPACITORS ON THE SAME CHIP
A device with a vertical transistor and a metal-insulator-metal (MIM) capacitor on a same substrate includes a vertical transistor including a bottom...
2018/0204832 APPROACH TO FABRICATION OF AN ON-CHIP RESISTOR WITH A FIELD EFFECT TRANSISTOR
A method of forming a resistor adjacent to a fin field effect transistor on a substrate, including, forming a plurality of vertical fins on the substrate,...
2018/0204831 ADVANCED NODE COST REDUCTION BY ESD INTERPOSER
An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and...
2018/0204830 ELECTRO-STATIC DISCHARGE ASSEMBLY, ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY PANEL
An electro-static discharge assembly, an array substrate and a fabrication method thereof, and a display panel are provided. The electro-static discharge...
2018/0204829 ARRAY SUBSTRATE AND DISPLAY DEVICE
An array substrate and a display device are disclosed. The array substrate includes a base substrate. The base substrate includes a pixel area and a peripheral...
2018/0204828 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first...
2018/0204827 ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE
An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor...
2018/0204826 3D MICRODISPLAY DEVICE AND STRUCTURE
A 3D micro display, the micro display including: a first single crystal layer including at least one LED driving circuit; and a second single crystal layer...
2018/0204825 CHIP INTEGRATION MODULE, CHIP PACKAGE STRUCTURE, AND CHIP INTEGRATION METHOD
The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die...
2018/0204824 ELECTRONIC MODULE AND SEMICONDUCTOR PACKAGE DEVICE
An electronic module includes a first sub-module and a second sub-module. The first sub-module includes a first substrate, a first electronic component...
2018/0204822 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure....
2018/0204821 SUBSTRATES, ASSEMBLES, AND TECHNIQUES TO ENABLE MULTI-CHIP FLIP CHIP PACKAGES
Substrates, assemblies, and techniques for enabling multi-chip flip chip packages are disclosed herein. For example, in some embodiments, a package substrate...
2018/0204820 3D THIN PROFILE PRE-STACKING ARCHITECTURE USING RECONSTITUTION METHOD
Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package...
2018/0204819 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
Input and output terminals are arranged so as to be adapted for an environment in which they are to be used. A semiconductor module (5) is surface-mounted on a...
2018/0204818 MANUFACTURING METHOD FOR PACKAGE DEVICE
A manufacturing method for a package device includes a chip preparation step of preparing a device chip that includes an adhesive layer, a mounting substrate...
2018/0204817 PACKAGE SUBSTRATE AND PACKAGE
A package substrate including a carrier, a first patterned conductive layer, a second patterned conductive layer and a 3D-printing conductive wire is provided....
2018/0204816 Packaging through Pre-Formed Metal Pins
A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of...
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