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Patent # Description
2018/0204815 Package Substrates, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The...
2018/0204814 METHOD FOR PREPARING A SEMICONDUCTOR PACKAGE
The present disclosure provides a method far preparing a semiconductor package. The semiconductor package includes a semiconductor device having an upper...
2018/0204813 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device includes: a redistribution line provided on a main face of a first semiconductor chip; an insulating film covering a front face of the...
2018/0204812 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural...
2018/0204811 SEMICONDUCTOR ELEMENT
A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface,...
2018/0204810 Chip-on-Substrate Packaging on Carrier
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a...
2018/0204809 SEMICONDUCTOR PACKAGE STRUCTURE FOR IMPROVING DIE WARPAGE AND MANUFACTURING METHOD THEREOF
A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of...
2018/0204808 Semiconductor Device with Circumferential Structure and Method of Manufacturing
A circumferential embedded structure is formed by laser irradiation in a semiconductor substrate, which is of a semiconductor material. The embedded structure...
2018/0204807 SEMICONDUCTOR DEVICE
A semiconductor device includes: a circuit board including a substrate made of an inorganic material, and a resin insulating layer formed on the substrate; a...
2018/0204806 MULTIPLE DRIVER PIN INTEGRATED CIRCUIT STRUCTURE
An integrated circuit (IC) structure includes a plurality of driver pins, each driver pin positioned at a driver pin level and oriented in a driver pin...
2018/0204805 COMPOSITE MAGNETIC SEALING MATERIAL AND ELECTRONIC CIRCUIT PACKAGE USING THE SAME AS MOLD MATERIAL
Disclosed herein is a composite magnetic sealing material includes a resin material and a filler blended in the resin material in a blend ratio of 50 vol. % or...
2018/0204804 ELECTROMAGNETIC SHIELDING FOR INTEGRATED CIRCUIT MODULES
The present disclosure provides electromagnetic shielding for integrated circuit modules with a module-bottom sealing procedure. First a precursor package with...
2018/0204803 INTERCONNECT STRUCTURE WITH NITRIDED BARRIER
Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a...
2018/0204802 WIRING BOARD HAVING COMPONENT INTEGRATED WITH LEADFRAME AND METHOD OF MAKING THE SAME
A wiring board includes an electronic component laterally surrounded by a leadframe, and first and second buildup circuitries disposed beyond the space...
2018/0204801 Method of Forming an Interconnect Structure Having an Air Gap and Structure Thereof
A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first...
2018/0204800 MULTI-LEVEL METALLIZATION INTERCONNECT STRUCTURE
A semiconductor structure is provided that includes a contact structure containing a gouged upper surface embedded in at least a middle-of-the-line (MOL)...
2018/0204799 CONDUCTIVE STRUCTURES, SYSTEMS AND DEVICES INCLUDING CONDUCTIVE STRUCTURES AND RELATED METHODS
Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via...
2018/0204798 INCREASED CONTACT ALIGNMENT TOLERANCE FOR DIRECT BONDING
A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and...
2018/0204797 BOTTOM-UP SELECTIVE DIELECTRIC CROSS-LINKING TO PREVENT VIA LANDING SHORTS
Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure...
2018/0204796 EMBEDDED METAL-INSULATOR-METAL (MIM) DECOUPLING CAPACITOR IN MONOLITIC THREE-DIMENSIONAL (3D) INTEGRATED...
Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure...
2018/0204795 Coarse Grid Design Methods and Structures
A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance...
2018/0204794 REDUCING TIP-TO-TIP DISTANCE BETWEEN END PORTIONS OF METAL LINES FORMED IN AN INTERCONNECT LAYER OF AN...
Aspects for reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) are provided. In one...
2018/0204793 PRINTED CIRCUIT BOARD AND ELECTRONIC EQUIPMENT
A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a...
2018/0204792 WORK PIECES AND METHODS OF LASER DRILLING THROUGH HOLES IN SUBSTRATES USING AN EXIT SACRIFICIAL COVER LAYER
Work pieces and methods of forming through holes in substrates are disclosed. In one embodiment, a method of forming a through hole in a substrate by drilling...
2018/0204791 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor package device, which includes an interposer die. The interposer die includes a semiconductor substrate and a...
2018/0204790 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a semiconductor device includes preparing a chip mounting part and a lead frame including leads arranged around the chip mounting...
2018/0204789 THYRISTOR AND THERMAL SWITCH DEVICE AND ASSEMBLY TECHNIQUES THEREFOR
A device may include a lead frame, where the lead frame includes a central portion, and a side pad, the side pad being laterally disposed with respect to the...
2018/0204788 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device PKG includes a semiconductor chip CP, a lead LD3, a wire BW5 electrically connecting a pad electrode PD2 of the semiconductor chip CP to...
2018/0204787 LEAD FRAME AND METHOD FOR MANUFACTURING THE SAME
A lead frame has a concavity formed on the upper-surface side of a metal plate and columnar portions 3 defined by the concavity. A horizontally deepest portion...
2018/0204786 DIE WITH METALLIZED SIDEWALL AND METHOD OF MANUFACTURING
The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each...
2018/0204785 HIGH-FREQUENCY DEVICE AND MANUFACTURING METHOD THEREOF
A high-frequency device manufacturing method is provided. The method includes providing a substrate; forming a conductive material on the substrate; standing...
2018/0204784 SEMICONDUCTOR DEVICE, INVERTER DEVICE, AND VEHICLE
The object is to provide a technology capable of enhancing a cooling performance of a semiconductor device. The semiconductor device includes a fin portion...
2018/0204783 EMI SHIELDING STRUCTURE HAVING HEAT DISSIPATION UNIT AND METHOD FOR MANUFACTURING THE SAME
An electromagnetic interference shielding structure is disclosed. The electromagnetic interference shielding structure includes an insulating member covering...
2018/0204782 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In a semiconductor device, an outer peripheral case body has guiding portions formed therein as a plurality of recesses. The plurality of guiding portions each...
2018/0204781 HIGH-FREQUENCY MODULE
A high-frequency module la includes: a wiring substrate 2; a plurality of components 3a and 3b that are mounted on an upper surface 2a of the wiring substrate...
2018/0204780 Package with Tilted Interface between Device Die and Encapsulating Material
A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface...
2018/0204779 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
To enhance the reliability of a semiconductor device. A semiconductor device is provided that includes a semiconductor element having a first pad, a frame...
2018/0204778 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE PROVIDED WITH SAME
It is an object of the present invention to provide a semiconductor device which allows an increase in the number of semiconductor elements mounted in parallel...
2018/0204777 METHOD OF PROCESSING SUBSTRATE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME
Disclosed are a method of processing a substrate and a method of fabricating a semiconductor device using the same. The method of processing a substrate...
2018/0204776 BACKSIDE PROCESSED SEMICONDUCTOR DEVICE
A semiconductor device includes a first substrate having a first surface and a second surface opposite to the first surface, a shallow trench isolation in the...
2018/0204775 UNIFORM SHALLOW TRENCH ISOLATION
A method for forming a field-effect transistor (FET) including forming a plurality of individual fins on a substrate. The method continues with forming a dummy...
2018/0204774 UNIFORM SHALLOW TRENCH ISOLATION
A method for forming a field-effect transistor (FET) including forming a plurality of individual fins on a substrate. The method continues with forming a dummy...
2018/0204773 MEMORY SYSTEM PERFORMING TRAINING OPERATION
A memory system may include a nonvolatile memory device and a controller. The nonvolatile memory device may include a data area and a device information area,...
2018/0204772 SYSTEMS AND METHODS FOR CONTROLLING RELEASE OF TRANSFERABLE SEMICONDUCTOR STRUCTURES
The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a...
2018/0204771 METHOD OF PROCESSING A SUBSTRATE
A method of processing a substrate, having a first surface with at least one division line formed thereon and a second surface opposite the first surface,...
2018/0204770 REMOVABLE TEMPORARY PROTECTIVE LAYERS FOR USE IN SEMICONDUCTOR MANUFACTURING
A method for temporarily protecting a semiconductor device wafer during processing includes preparing a solution including poly(vinyl alcohol) and water,...
2018/0204769 LOW TEMPERATURE POLY SILICON BACKBOARD, METHOD FOR MANUFACTURING THE SAME AND LIGHT-EMITTING DEVICE
The present disclosure provides a Low Temperature Poly Silicon (LTPS) backboard, a method for manufacturing the LTPS, and a light-emitting device. The LTPS...
2018/0204768 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Described herein is a technique capable of forming a film having excellent step coverage and superior filling properties. According to the technique, there is...
2018/0204767 SACRIFICIAL LAYER FOR PLATINUM PATTERNING
In accordance with at least one embodiment of the disclosure, a method of patterning platinum on a substrate is disclosed. In an embodiment, an adhesive layer...
2018/0204766 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD
A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating...
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