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Patent # Description
2018/0203806 VARIABLE TRANSLATION-LOOKASIDE BUFFER (TLB) INDEXING
A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a...
2018/0203805 COMPUTER AND MEMORY REGION MANAGEMENT METHOD
A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS...
2018/0203804 FIRMWARE OR HARDWARE COMPONENT ASSIST FOR MEMORY MAPPED I/O
A method is provided for providing access to a data block in a device of a processing system. The device is connected to a processor of the processing system...
2018/0203803 MANAGING AND SHARING ALIAS DEVICES ACROSS LOGICAL CONTROL UNITS
Aspects include a computer-implemented method for managing alias devices across logical control units. Aspects include establishing one or more alias...
2018/0203802 CACHE APPARATUS AND A METHOD OF CACHING DATA
A cache apparatus is provided comprising a data storage structure providing N cache ways that each store data as a plurality of cache blocks. The data storage...
2018/0203801 MANAGING MEMORY FOR SECURE ENCLAVES
A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an...
2018/0203800 USING A DIRECTORY-BASED CACHE COHERENCE SYSTEM TO REGULATE SNOOPING
A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence...
2018/0203799 MEMORY-EFFICIENT LAST LEVEL CACHE ARCHITECTURE
A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level...
2018/0203798 QUALITY-OF-SERVICE MONITORING IN A CACHE
A cache to provide data caching in response to data access requests from at least one system device, and a method operating such a cache, are provided....
2018/0203797 Compression and Decompression of Data at High Speed in Solid State Storage
Compression and decompression of data at high speed in solid state storage is described, including accessing a compressed data comprising a plurality of blocks...
2018/0203796 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
A nonvolatile memory device includes control logic and a memory cell array. The memory cell array includes a first plane and a second plane. The control logic...
2018/0203795 TRACE MANAGEMENT
Systems, methods, and computer program products for trace management in a distributed computing environment are described. A trace manager receives a request...
2018/0203794 METHODS AND SYSTEMS OF DISTRIBUTED TRACING
A system and methods are provided for distributed tracing in a distributed application. In one embodiment, a method includes observing a plurality of messages...
2018/0203793 INTELLIGENT DEVICE SELECTION FOR MOBILE APPLICATION TESTING
A computer-implemented facility is provided for intelligent mobile device selection for mobile application testing. The computer-implemented facility...
2018/0203792 INTELLIGENT DEVICE SELECTION FOR MOBILE APPLICATION TESTING
A computer-implemented facility is provided for intelligent mobile device selection for mobile application testing. The computer-implemented facility...
2018/0203791 MULTI ENVIRONMENT AWARE DEBUGGER
Stepwise execution of different instances of an application can be initiated, in parallel, in different computing environments. Responsive to an execution step...
2018/0203790 DETECTION OF SOFTWARE ERRORS
A method, executed by a computer, includes repeatedly collecting execution information for a code unit to produce collected execution information for the code...
2018/0203789 INTELLIGENT PROCESSING OF DISTRIBUTED BREAKPOINTS
A method for processing distributed breakpoints when debugging a distributed application includes establishing a breakpoint in source code of a distributed...
2018/0203788 MULTI ENVIRONMENT AWARE DEBUGGER
Stepwise execution of different instances of an application can be initiated, in parallel, in different computing environments. Responsive to an execution step...
2018/0203787 DETECTION OF SOFTWARE ERRORS
A method, executed by a computer, includes repeatedly collecting execution information for a code unit to produce collected execution information for the code...
2018/0203786 PERFORMANCE DIAGNOSTICS VIA OFFLINE REPLAY
Methods and systems for performance measurements of a program are provided. An execution trace of the program may be captured and stored. The stored execution...
2018/0203785 PERFORMANCE OF A SYSTEM INCLUDING A FIRST PROCESSOR AND A SECOND PROCESSOR
A method for improving performance of a system including a first processor and a second processor includes obtaining a code region specified to be executed on...
2018/0203784 MANAGEMENT COMPUTER AND PERFORMANCE DEGRADATION SIGN DETECTION METHOD
A management computer detecting signs of performance degradation even when virtual computing units are generated and destroyed repeatedly over a short period...
2018/0203783 PERFORMANCE OF A SYSTEM INCLUDING A FIRST PROCESSOR AND A SECOND PROCESSOR
A method for improving performance of a system including a first processor and a second processor includes obtaining a code region specified to be executed on...
2018/0203782 PASSIVE DEVICE DETECTION
A system for passive device identification includes a passive device communicatively coupled to a processing device. The processing device includes a passive...
2018/0203781 METHODS FOR UPDATING MEMORY MAPS OF A SYSTEM-ON-CHIP
This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the...
2018/0203780 EFFICIENT BREAKPOINT DETECTION VIA CACHES
Efficient breakpoint detections via caches comprises monitoring a memory location by detecting cache misses on a cache. A memory address that is to be...
2018/0203779 BUS HANG DETECTION AND FIND OUT
A method of monitoring I2C bus status using a Baseboard Management Controller (BMC) and a hardware watchdog (HW) circuit is provided. The method includes...
2018/0203778 PERIODIC NON-INTRUSIVE DIAGNOSIS OF LOCKSTEP SYSTEMS
Aspects disclosed herein relate to periodic non-intrusive diagnosis of lockstep systems. An exemplary method includes comparing execution of a program on a...
2018/0203777 Method of Phase Calibration for Double Data Rate Memory Interface and Related System
A method of phase calibration for a system to control a double data rate memory device includes setting a scanning frequency at an initial value to determining...
2018/0203776 NON-MONOTONIC EVENTUAL CONVERGENCE FOR DESIRED STATE CONFIGURATION
Technologies are provided for non-monotonic eventual convergence for desired state configuration ("DSC"). In some situations DSC cannot move toward a desired...
2018/0203775 MEMORY MODULE, MEMORY SYSTEM INCLUDING THE SAME AND OPERATION METHOD THEREOF
A memory module may include a first memory module comprising a plurality of first memory devices each having an extra memory region, a second memory module...
2018/0203774 IDENTIFYING A FAILING GROUP OF MEMORY CELLS IN A MULTI-PLANE STORAGE OPERATION
An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory that includes multiple memory cells arranged...
2018/0203773 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
An information processing apparatus, includes: a memory; and a processor: monitors whether communication with a first information processing apparatus coupled...
2018/0203772 ELECTRONIC EQUIPMENT INCLUDING STORAGE DEVICE
According to one embodiment, a storage device includes a nonvolatile memory, controller and interface. The nonvolatile memory stores data. The controller...
2018/0203771 Database Redo Log Optimization by Skipping MVCC Redo Log Records
Restoring of a database table in the database system (e.g., an in-memory insert-only database system, etc.) is initiated. Thereafter, a transaction log volume...
2018/0203770 Including Metadata in Data Resources
A server system comprising: a respective storage area for each of a plurality of respective parties including a first party and a second party, and a manager...
2018/0203769 Reliability Enhancement in a Distributed Storage System
Machines, systems and methods for enhancing data recovery in a data storage system, the method comprising determining whether one or more data storage mediums...
2018/0203768 SYSTEM RECOVERY USING WOL
The present technology provides a system and method for smartly resetting a hang device of a server system based upon a Wake-on-Lan (WoL) message and status of...
2018/0203767 METHOD AND APPARATUS FOR JOB OPERATION RETRY
Embodiments of the present application provide operation retry methods and apparatuses. One exemplary method includes: detecting whether an operation of a job...
2018/0203766 PARALLEL DATA COLLECTION AND RECOVERY FOR FAILING VIRTUAL COMPUTER PROCESSING SYSTEM
Techniques for parallel data collection and recovery for a failing virtual processing system are disclosed. According to aspects of the present disclosure, an...
2018/0203765 RAID SYSTEMS AND METHODS FOR IMPROVED DATA RECOVERY PERFORMANCE
A RAID system includes a storage enclosure comprising a plurality of independent data storage devices. A processor is associated with the storage enclosure....
2018/0203764 USING PARITY DATA FOR CONCURRENT DATA AUTHENTICATION, CORRECTION, COMPRESSION, AND ENCRYPTION
A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes...
2018/0203763 FIRST READ SOLUTION FOR MEMORY
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when...
2018/0203762 FIRST READ SOLUTION FOR MEMORY
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when...
2018/0203761 TARGETED ALIASING SINGLE ERROR CORRECTION (SEC) CODE
A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix...
2018/0203760 MEMORY SYSTEM AND OPERATION METHOD THEREOF
A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks; and a controller suitable for checking a read operation time,...
2018/0203759 Memory Error Detection
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an...
2018/0203758 INTELLIGENT REFRESH OF 3D NAND
A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks...
2018/0203757 LOG MESSAGE GROUPING APPARATUS, LOG MESSAGE GROUPING SYSTEM, AND LOG MESSAGE GROUPING METHOD
A log message grouping apparatus calculates a coincidence degree evaluation value E1 representing the degree of coincidence between minority words, which are...
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