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Patent # Description
2018/0211990 SOLID-STATE IMAGING ELEMENT AND IMAGING DEVICE
To improve detection efficiency in a solid-state imaging element including a SPAD in which an electrode and wiring are placed in a central portion. A...
2018/0211989 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS
The present technology relates to a semiconductor device providing an image sensor package capable of coping with an increase in the number of I/Os of an image...
2018/0211988 SOLID STATE IMAGING DEVICE
A solid state imaging device includes: a pixel array unit in which same-color pixels corresponding to each of a plurality of colors configured to convert...
2018/0211987 SOLID-STATE IMAGING DEVICE AND DRIVING METHOD THEREOF, AND ELECTRONIC APPARATUS
The present technology relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus that make it possible to improve the...
2018/0211986 IMAGE SENSOR AND MANUFACTURING METHOD THEREOF
An image sensor includes a semiconductor layer, a plurality of light sensing regions, a first pixel isolation layer, a light shielding layer, and a wiring...
2018/0211985 ARRAY SUBSTRATES AND THE MANUFACTURING METHODS THEREOF, AND DISPLAY DEVICES
The present disclosure relates to a manufacturing method of array substrates, wherein a second masking process forming an active layer, a source electrode and...
2018/0211983 Array Substrate and Display Device
The present disclosure discloses an array substrate and a display device. The array substrate includes: a substrate; and a plurality of data lines and a...
2018/0211982 DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL
A display substrate, a manufacturing method thereof, and a display panel are provided. The display substrate includes a base substrate, a display region on the...
2018/0211981 TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
A TFT array substrate and its manufacturing method are disclosed. The TFT array substrate includes a substrate having a display area and a non-display area,...
2018/0211980 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a...
2018/0211979 LIGHT EMITTING DISPLAY DEVICE
A light emitting display device according to an exemplary embodiment of the present disclosure includes: a first substrate; an insulating layer disposed on the...
2018/0211978 LOW TEMPERATURE POLYSILICON ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
A low temperature polysilicon array substrate and a method for manufacturing the same are disclosed. The method includes forming a light shield layer, a buffer...
2018/0211977 FLEXIBLE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
A flexible display device includes a flexible substrate, an adhesion layer disposed on a surface of the flexible substrate, and a plurality of pixel structures...
2018/0211976 SIGNAL LINE STRUCTURE, ARRAY SUBSTRATE, AND DISPLAY DEVICE
Embodiments of the disclosure relate to a signal line structure, an array substrate, and a display device, where the signal line structure includes a plurality...
2018/0211975 CONNECTION STRUCTURE, ARRAY SUBSTRATE, AND DISPLAY DEVICE
Disclosed are a connection structure, an array substrate, and a display device. A connection structure according to some embodiments of the application...
2018/0211974 DISPLAY PANEL AND DISPLAY DEVICE
The present disclosure provides a display panel which includes a display panel body, a first data line driving circuit and a second data line driving circuit...
2018/0211973 Butted Body Contact for SOI Transistor
Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower...
2018/0211972 Systems, Methods and Apparatus for Enabling High Voltage Circuits
Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in ...
2018/0211971 NON-VOLATILE MEMORY DEVICE
According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first...
2018/0211970 THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED DRAIN SIDE SELECT GATE ELECTRODES AND METHOD OF MAKING THEREOF
A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack...
2018/0211969 DISCRETE CHARGE TRAPPING ELEMENTS FOR 3D NAND ARCHITECTURE
A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides,...
2018/0211968 Vertical Memory Devices And Methods Of Manufacturing The Same
A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of...
2018/0211967 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third...
2018/0211966 METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE
A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a ...
2018/0211965 MEMORY CELL, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED...
A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory...
2018/0211964 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads...
2018/0211963 FORMING eDRAM UNIT CELL WITH VFET AND VIA CAPACITANCE
A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor)...
2018/0211962 SEMICONDUCTOR DEVICE
A semiconductor device and method of manufacturing are provided. The semiconductor device includes a substrate; first and second structures spaced apart from...
2018/0211961 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor memory device and a manufacturing method thereof are provided in the present invention. Storage node contacts are formed on a semiconductor...
2018/0211960 SEMICONDUCTOR DEVICE HAVING FIN-SHAPED STRUCTURE AND BUMP
A semiconductor device includes a substrate having a first region and a second region, a fin-shaped structure and a bump on the first region of the substrate,...
2018/0211959 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, first through fourth gate electrodes, and first through fifth fin active pattern. A first recess which is formed...
2018/0211958 SEMICONDUCTOR APPARATUS
A semiconductor apparatus includes a high side region and a low side region, wherein the high side region includes semiconductor devices, and those...
2018/0211957 LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an...
2018/0211956 SEMICONDUCTOR DEVICE
Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a...
2018/0211955 Fin Cut to Prevent Replacement Gate Collapse on STI
The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a...
2018/0211954 ASYMMETRIC VARACTOR
An accumulation-mode MOS varactor is formed with a standard CMOS process and having an anti-symmetric-CV curve. The asymmetric varactor (ASVAR) can efficiently...
2018/0211953 INTEGRATED PACKAGING STRUCTURE
An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a...
2018/0211952 SEMICONDUCTOR DEVICE INCLUDING RESISTOR STRUCTURE
Provided is a semiconductor device having an enhanced characteristic and a resistor structure satisfying a desired target resistor value of a resistor device....
2018/0211951 DRAIN-EXTENDED METAL-OXIDE-SEMICONDUCTOR BIPOLAR SWITCH FOR ELECTRICAL OVERSTRESS PROTECTION
High voltage drain-extended metal-oxide-semiconductor (DEMOS) bipolar switches for electrical overstress protection are provided. In certain configurations...
2018/0211950 SEMICONDUCTOR DEVICES WITH ELECTROSTATIC DISCHARGE ROBUSTNESS
An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed...
2018/0211949 SEMICONDUCTOR DEVICE
A semiconductor device includes a MOS transistor which is coupled between two terminals and discharges current which flows caused by generation of static...
2018/0211948 STANDARD CELL ARCHITECTURE WITH AT LEAST ONE GATE CONTACT OVER AN ACTIVE AREA
A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of...
2018/0211947 STANDARD CELL ARCHITECTURE WITH AT LEAST ONE GATE CONTACT OVER AN ACTIVE AREA
A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of...
2018/0211946 Integrated DRAM with Low-Voltage Swing I/O
This document describes apparatuses and techniques for integrated DRAM with low-voltage swing I/O. In some aspects, a dynamic random access memory (DRAM) die...
2018/0211945 STACKED PIXEL STRUCTURES
A micro-transfer printed high-resolution inorganic light-emitting diode (iLED) display includes a display substrate and a plurality of pixels disposed over the...
2018/0211944 FAN-OUT SEMICONDUCTOR PACKAGE MODULE
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip with connection pads on its active surface...
2018/0211943 PACKAGE SUBSTRATE COMPRISING SIDE PADS ON EDGE, CHIP STACK, SEMICONDUCTOR PACKAGE, AND MEMORY MODULE COMPRISING...
The semiconductor package according to the present invention comprises: an integrated substrate; a bottom chip stack, which is mounted on the integrated...
2018/0211942 LIGHT-EMITTING DEVICE
A light-emitting device includes a substrate, a light-emitting component, a wavelength conversion component, an adhesive and a reflective layer. The...
2018/0211941 VERTICAL LIGHT EMITTING DIODE WITH MAGNETIC BACK CONTACT
A structure containing a vertical light emitting diode (LED) is provided. The vertical LED is present in an opening located in a display substrate, and the...
2018/0211940 A Colour Inorganic LED Display for Display Devices with a High Number of Pixel
An image generator for use in a display device, the image generator comprising: a plurality of ILED array chips each comprising a plurality of ILED emitters...
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