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Patent # Description
2018/0211939 EMBEDDED STACKED DIE PACKAGES AND RELATED METHODS
Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically...
2018/0211938 Power Module
It is an object of the present invention to provide a power module which can withstand a high voltage with a thin insulating layer. A power module of the...
2018/0211937 SEMICONDUCTOR PACKAGE
A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an...
2018/0211936 THIN FAN-OUT MULTI-CHIP STACKED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active...
2018/0211935 SURFACE MOUNTING SEMICONDUCTOR COMPONENTS
A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder...
2018/0211934 RESIN SUBSTRATE, COMPONENT-MOUNTED RESIN SUBSTRATE, METHOD OF MANUFACTURING RESIN SUBSTRATE, AND METHOD OF...
A component-mounted resin substrate includes a thermoplastic resin substrate and an electronic component. The resin substrate includes a surface including a...
2018/0211933 CONNECTING DEVICE AND CIRCUIT CHIP CONNECTING METHOD USING CONNECTING DEVICE
A connecting device for connecting a circuit chip to a substrate is provided. The connecting device includes: a main body having a first opening and a second...
2018/0211932 METHOD AND SYSTEM FOR AUTOMATIC BOND ARM ALIGNMENT
A method, as well as a system implementing the method, for automatically aligning a bond arm with respect to a bonding support surface for supporting a...
2018/0211931 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit...
2018/0211930 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method of manufacturing a semiconductor device including: bonding a wire constituted of copper on an electrode pad provided on a surface of a semiconductor...
2018/0211929 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor...
2018/0211928 Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a...
2018/0211927 RELIABLE PAD INTERCONNECTS
A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad...
2018/0211926 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
Disclosed herein is a method of manufacturing a semiconductor package including a semiconductor chip sealed by a sealing synthetic resin. The method includes...
2018/0211925 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME
An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed...
2018/0211924 THIN 3D DIE WITH ELECTROMAGNETIC RADIATION BLOCKING ENCAPSULATION
After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the...
2018/0211923 Susceptor For Holding A Semiconductor Wafer Having An Orientation Notch, A Method For Depositing A Layer On A...
A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement...
2018/0211922 SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE STRUCTURE HAVING NUCLEATION STRUCTURE AND METHOD OF FORMING THE SAME
A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern...
2018/0211921 INTERCONNECT STRUCTURE AND FABRICATING METHOD THEREOF
An interconnect structure including a substrate and a conductive pattern is provided. The conductive pattern includes a bottom portion. The bottom portion of...
2018/0211920 HYBRID DIELECTRIC SCHEME FOR VARYING LINER THICKNESS AND MANGANESE CONCENTRATION
A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner....
2018/0211919 SEMICONDUCTOR DEVICE
A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region,...
2018/0211918 COBALT BASED INTERCONNECTS AND METHODS OF FABRICATION THEREOF
An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the...
2018/0211917 SEMICONDUCTOR MODULE COMPRISING TRANSISTOR CHIPS, DIODE CHIPS AND DRIVER CHIPS ARRANGED IN A COMMON PLANE
A semiconductor module is disclosed. In one example, the module includes a carrier, at least one semiconductor transistor disposed on the carrier, at least one...
2018/0211916 METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface,...
2018/0211915 CONNECTING BAR
A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive...
2018/0211914 Power Distribution
An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that...
2018/0211913 CROSS-POINT ARRAY DEVICE INCLUDING CONDUCTIVE FUSE MATERIAL LAYER
A cross-point array device includes a pillar-shaped structure disposed in an intersection region where a first conductive line overlaps a second conductive...
2018/0211912 Raised Via for Terminal Connections on Different Planes
A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom...
2018/0211911 METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER
A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer...
2018/0211910 VARIABLE RESISTANCE MEMORY DEVICES
A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable...
2018/0211909 PACKAGE SUBSTRATE, METHOD FOR FABRICATING THE SAME, AND PACKAGE DEVICE INCLUDING THE PACKAGE SUBSTRATE
A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern...
2018/0211908 PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME
A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A...
2018/0211907 SEMICONDUCTOR PACKAGE WITH HEAT SLUG AND RIVET FREE DIE ATTACH AREA
A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower...
2018/0211906 DISPLAY DEVICE
A display device is disclosed. In one aspect, the display device includes a substrate including a display area configured to display an image and a peripheral...
2018/0211905 SEMICONDUCTOR PACKAGE HAVING A LEADFRAME WITH MULTI-LEVEL ASSEMBLY PADS
A leadframe (100) comprises a frame (101) of sheet metal in a first planar level, where the frame has metallic leads (110) and a first metallic pad (120)...
2018/0211904 INTERDIGIT DEVICE ON LEADFRAME FOR EVENLY DISTRIBUTED CURRENT FLOW
The disclosure is directed to techniques to evenly distribute current in interdigited leadframes by decoupling current between interdigited pads. The leadframe...
2018/0211903 PREFORMED LEAD FRAME AND LEAD FRAME PACKAGED STRUCTURE INCLUDING THE SAME
A preformed lead frame includes a metallic substrate, a plurality of spaced-apart conductive lead frame units and intersecting trenches, a molding layer, and a...
2018/0211901 Interconnect Structure for Package-on-Package Devices and a Method of Fabricating
An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon...
2018/0211900 Techniques For Fluid Cooling Of Integrated Circuits In Packages
A method is provided for removing heat from an integrated circuit package. Fluid coolant is provided from a fluid inlet of a fluid routing device through...
2018/0211899 Efficient Heat Removal From Component Carrier With Embedded Diode
A component carrier has an interconnected stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer...
2018/0211898 Semiconductor Device, Vehicle-Mounted Semiconductor Device, and Vehicle-Mounted Control Device
Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device...
2018/0211897 HETEROJUNCTION BIPOLAR TRANSISTOR POWER AMPLIFIER WITH BACKSIDE THERMAL HEATSINK
A heterojunction bipolar transistor may include an emitter, a base contacting the emitter, a collector contacting the base, a sub-collector contacting the...
2018/0211896 PACKAGED SEMICONDUCTOR COMPONENTS HAVING SUBSTANTIALLY RIGID SUPPORT MEMBERS AND METHODS OF PACKAGING...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
2018/0211895 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric...
2018/0211894 ON-CHIP COMBINED HOT CARRIER INJECTION AND BIAS TEMPERATURE INSTABILITY MONITOR
Methods and circuits for monitoring circuit degradation include measuring degradation in a set of on-chip test oscillators that vary according to a quantity...
2018/0211893 VACUUM PROCESSING APPARATUS
A sample stage which is disposed inside a vacuum processing chamber and on which a wafer to be processed is placed on an upper surface thereof includes a...
2018/0211892 PREVENTION OF CHARGING DAMAGE IN FULL-DEPLETION DEVICES
Methods for checking a semiconductor device for compliance with a rule include determining one or more device type categories to which a semiconductor device...
2018/0211891 VIRTUAL METROLOGY SYSTEMS AND METHODS FOR USING FEEDFORWARD CRITICAL DIMENSION DATA TO PREDICT OTHER CRITICAL...
A controller includes a memory that stores a first model corresponding to a first critical dimension of a substrate processed by a substrate processing system...
2018/0211890 Electrically Testable Microwave Integrated Circuit Packaging
An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final "non-flip chip" circuit...
2018/0211889 CLEAVE SYSTEMS, MOUNTABLE CLEAVE MONITORING SYSTEMS, AND METHODS FOR SEPARATING BONDED WAFER STRUCTURES
Cleave systems for separating bonded wafer structures, mountable cleave monitoring systems and methods for separating bonded wafer structures are disclosed. In...
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