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Patent # Description
2018/0211888 Array Substrate and Manufacturing Method Thereof
An array substrate and a manufacturing method thereof are provided. The method for manufacturing the array substrate includes: forming a passivation layer on a...
2018/0211887 SEMICONDUCTOR DEVICE
A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the...
2018/0211886 MANUFACTURING METHOD FOR DUAL WORK-FUNCTION METAL GATES
A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a high dielectric constant (high-k) gate dielectric...
2018/0211885 FORMATION OF COMMON INTERFACIAL LAYER ON Si/SiGe DUAL CHANNEL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial...
2018/0211884 SILICON AND SILICON GERMANIUM NANOWIRE FORMATION
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more...
2018/0211883 VERTICAL FIELD EFFECT TRANSISTOR HAVING U-SHAPED TOP SPACER
A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer...
2018/0211882 SEMICONDUCTOR DEVICE COMPRISING A SWITCH
A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell...
2018/0211881 SELF-ALIGNED EPI CONTACT FLOW
Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion...
2018/0211880 MULTIPLE FINFET FORMATION WITH EPITAXY SEPARATION
A method for forming a semiconductor device includes: forming a plurality of fins from a substrate; removing at least one fin to form at least a first group of...
2018/0211879 STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE
A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the...
2018/0211878 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first bidirectional switch element including a first gate electrode, a second gate electrode, a first electrode, and a...
2018/0211877 METHOD OF PROCESSING A WAFER AND WAFER PROCESSING SYSTEM
A method of processing a wafer having a plurality of devices partitioned by division lines, including attaching the wafer to an adhesive tape supported by a...
2018/0211876 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY APPARATUS
The present disclosure belongs to the field of display and discloses an array substrate and a method for manufacturing the same, and a display apparatus. The...
2018/0211875 FABRICATION OF SELF-ALIGNED GATE CONTACTS AND SOURCE/DRAIN CONTACTS DIRECTLY ABOVE GATE ELECTRODES AND...
A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the...
2018/0211874 FABRICATION OF SELF-ALIGNED GATE CONTACTS AND SOURCE/DRAIN CONTACTS DIRECTLY ABOVE GATE ELECTRODES AND...
A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the...
2018/0211873 RECESSING OF LINER AND CONDUCTOR FOR VIA FORMATION
The disclosure relates to integrated circuit (IC) fabrication techniques. Methods according to the disclosure can include: forming a reaction layer on the...
2018/0211872 ENHANCED COBALT AGGLOMERATION RESISTANCE AND GAP-FILL PERFORMANCE BY RUTHENIUM DOPING
In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate...
2018/0211871 SELF-ALIGNED VIA FORMING TO CONDUCTIVE LINE AND RELATED WIRING STRUCTURE
A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a...
2018/0211870 INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings...
2018/0211869 DESIGN-AWARE PATTERN DENSITY CONTROL IN DIRECTED SELF-ASSEMBLY GRAPHOEPITAXY PROCESS
A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer...
2018/0211868 Methods for Isolating Portions of a Loop of Pitch-Multiplied Material and Related Structures
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is...
2018/0211867 METHOD FOR MANUFACTURING DUAL DAMASCENE STRUCTURES
A method for manufacturing dual damascene structures is provided with the steps of forming a via hole through a dielectric layer, forming a sacrificial layer...
2018/0211866 FORMING SACRIFICIAL ENDPOINT LAYER FOR DEEP STI RECESS
A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a substrate, forming one or more shallow...
2018/0211865 SOL GEL COATED SUPPORT RING
A support member for a thermal processing chamber is described. The support member has a sol coating on at least one surface. The sol coating contains a...
2018/0211864 OPTIMIZED LOW ENERGY / HIGH PRODUCTIVITY DEPOSITION SYSTEM
A mechanical indexer for a substrate processing tool includes first and second arms each having first and second end effectors. The first arm is configured to...
2018/0211863 APPARATUS AND METHODS FOR WAFER CHUCKING ON A SUSCEPTOR FOR ALD
Described are apparatus and methods for processing a semiconductor wafer so that the wafer remains in place during processing. The wafer is subjected to a...
2018/0211862 MOMENT CANCELLING PAD RAISING MECHANISM IN WAFER POSITIONING PEDESTAL FOR SEMICONDUCTOR PROCESSING
An assembly used in a process chamber for depositing a film on a wafer including a pedestal assembly having a pedestal movably mounted to a main frame. A lift...
2018/0211861 METHOD FOR PROCESSING A HOLDING PLATE, IN PARTICULAR FOR A CLAMP FOR HOLDING A WAFER
A method for processing a holding plate (10) of a clamping device (in particular clamp wafer chuck) for holding a component, in particular a wafer, wherein the...
2018/0211860 WAFER CASSETTE
A wafer cassette for storing wafers comprises a case and a plurality of carriers for carrying the wafers. Each of the carriers is pivotally and movably mounted...
2018/0211859 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
During a teaching operation regarding a transport mechanism, a hand of the transport mechanism is moved to a tentative target position in a substrate...
2018/0211858 SUBSTRATE TRANSPORT APPARATUS
A transport apparatus including a drive section connected to a frame and including a multi-drive shaft spindle, with at least one coaxial shaft spindle, more...
2018/0211857 APPARATUS FOR STORING AND HANDLING ARTICLE AT CEILING
Disclosed herein is an apparatus for storing and handling an article at a ceiling, including: an internal rail configured to hang on the ceiling; a storage...
2018/0211856 APPARATUS FOR ELECTROCHEMICALLY PROCESSING SEMICONDUCTOR SUBSTRATES
An apparatus for processing a front face of a semiconductor wafer is provided. The apparatus includes a main chamber, at least one loading port connected to...
2018/0211855 SUBSTRATE HEATING APPARATUS, SUBSTRATE HEATING METHOD AND METHOD OF MANUFACTURING ELECTRONIC DEVICE
To provide a substrate heating apparatus, a substrate heating method and a method of manufacturing an electronic device having excellent uniformity at the time...
2018/0211854 SYSTEM AND METHOD FOR HEAT TREATMENT OF SUBSTRATES
A system and/or method for heat treatment of substrates. The system includes a housing that defines a heating chamber and a door assembly that encloses an...
2018/0211853 SUBSTRATE PROCESSING APPARATUS, TEMPERATURE CONTROL METHOD, AND TEMPERATURE CONTROL PROGRAM
Disclosed is a substrate processing apparatus including: a placing table having a placement surface and provided with a heater in each divided region obtained...
2018/0211852 LASER PROCESSING APPARATUS
A laser processing apparatus includes: a chuck table that holds a packaged wafer; a laser beam applying unit that applies a pulsed laser beam to the packaged...
2018/0211851 CUTTING APPARATUS
A cutting apparatus includes a cutting unit including a cutting blade that has a cutting edge for cutting a dresser board. An elastic wave detection sensor is...
2018/0211850 SUBSTRATE TRANSFER CHAMBER, SUBSTRATE PROCESSING SYSTEM, AND METHOD FOR REPLACING GAS IN SUBSTRATE TRANSFER CHAMBER
A compartment variable device is provided with: a baffle plate which has a plurality of openings and which as a whole has a rectangular shape; a rectangular...
2018/0211849 SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD
The invention performs optimum processing even when process requirements vary in the middle of a substrate processing process. A method is provided whereby a...
2018/0211848 ELECTRONIC PRODUCT AND MANUFACTURING METHOD THEREOF
An electronic product including a supporting structure, a first thermo-formable film, a conductive circuit and a protection layer is provided. The conductive...
2018/0211847 Method for Attaching Wiring Protective Film Layer, Wiring Structure and Display Panel
The present disclosure provides a method for attaching a wiring protective film layer, a wiring structure and a display panel. The attaching method comprises:...
2018/0211846 LINER AND BARRIER APPLICATIONS FOR SUBTRACTIVE METAL INTEGRATION
Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve...
2018/0211845 METHODS OF MINIMIZING PLASMA-INDUCED SIDEWALL DAMAGE DURING LOW K ETCH PROCESSES
Methods for minimizing plasma-induced sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated...
2018/0211844 NATURALLY OXIDIZED FILM REMOVING METHOD AND NATURALLY OXIDIZED FILM REMOVING DEVICE
A technique capable of removing a natural oxide film formed on a surface of a semiconductor layer which contains a compound of indium and an element other than...
2018/0211843 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A technique capable of controlling in-plane uniformity of a film formed on a substrate includes a step of forming a film on a substrate by performing a...
2018/0211842 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING FORMING A DIELECTRIC LAYER ON A STRUCTURE HAVING A HEIGHT...
A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure...
2018/0211841 Copper Alloy Sputtering Target and Semiconductor Element Wiring
A first copper alloy sputtering target comprising 0.5 to 4.0 wt % of Al and 0.5 wtppm or less of Si and a second copper alloy sputtering target comprising 0.5...
2018/0211840 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM
There is provided a technology includes: heating a heat insulating plate, which is held by a substrate holder configured to hold a substrate, to a processing...
2018/0211839 CARBON DOPANT GAS AND CO-FLOW FOR IMPLANT BEAM AND SOURCE LIFE PERFORMANCE IMPROVEMENT
Ion implantation processes and systems are described, in which carbon dopant source materials are utilized to effect carbon doping. Various gas mixtures are...
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