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Patent # Description
2018/0218950 SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first...
2018/0218949 MULTIPLE GATE LENGTH VERTICAL FIELD-EFFECT-TRANSISTORS
Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a...
2018/0218948 INTEGRATING A PLANAR FIELD EFFECT TRANSISTOR (FET) WITH A VERTICAL FET
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a...
2018/0218947 METHODS, APPARATUS AND SYSTEM FOR PROVIDING ADJUSTABLE FIN HEIGHT FOR A FINFET DEVICE
A method and system are disclosed herein for an adjustable effective fin height in a gate region of a finFET device. Fin structures, each having a first...
2018/0218946 3D SEMICONDUCTOR DEVICE, FABRICATION METHOD AND SYSTEM
A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first...
2018/0218945 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the...
2018/0218944 SYSTEM FOR UNIFORM DEPOSITION OF METAL
A system includes a deposition chamber comprising first, second, and third stations, a delivery system providing a substrate to the deposition chamber, a...
2018/0218943 TECHNIQUES FOR FILLING A STRUCTURE USING SELECTRIVE SURFACE MODIFICATION
A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an...
2018/0218942 METHODS FOR FORMING A BARRIER LAYER WITH PERIODIC CONCENTRATIONS OF ELEMENTS AND STRUCTURES RESULTING THEREFROM
A method is provided which includes dispensing and removing different deposition solutions during an electroless deposition process to form different sub-films...
2018/0218941 SEMICONDUCTOR DEVICE
A semiconductor device includes a wiring substrate, a semiconductor chip, conductive paste, and an adhesive layer. The wiring substrate includes an insulating...
2018/0218940 CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a...
2018/0218939 Semiconductor Devices and Methods for Forming Semiconductor Devices
A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating...
2018/0218938 GATE ALL AROUND DEVICE ARCHITECTURE WITH HYBRID WAFER BOND TECHNIQUE
A system and method for fabricating non-planar devices while managing semiconductor processing yield and cost are described. A semiconductor device fabrication...
2018/0218937 BOND PAD PROTECTION FOR HARSH MEDIA APPLICATIONS
A method for making and a semiconductor device comprises a silicon die including a metal contact region and, at least one passivation layer covering the...
2018/0218936 Switch Element and Load Driving Device
It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an...
2018/0218935 SUBSTRATE TRANSPORT DEVICE, DETECTION POSITION CALIBRATION METHOD AND SUBSTRATE PROCESSING APPARATUS
During a detection position calibrating operation and a substrate transport operation, a detection coordinate calculator calculates detection coordinates of an...
2018/0218934 HANDLER BONDING AND DEBONDING FOR SEMICONDUCTOR DIES
Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one...
2018/0218933 ADJUSTABLE EXTENDED ELECTRODE FOR EDGE UNIFORMITY CONTROL
Embodiments described herein generally related to a substrate processing apparatus. In one embodiment, a process kit for a substrate processing chamber...
2018/0218932 PROCESSING METHOD OF WORKPIECE
A processing method for processing a workpiece includes a holding step of holding the front surface side of the workpiece on which an alignment mark is formed...
2018/0218931 PROCESSING APPARATUS
A processing apparatus includes a cassette rest unit from which a wafer is fed by an unloading unit and a feed unit to a plurality of processing units, in...
2018/0218930 SUBSTRATE PROCESSING APPARATUS
Provided is a substrate processing apparatus, which comprises a processing chamber, a substrate sensing assembly, a rotation shaft and a driving assembly. A...
2018/0218929 SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND STORAGE MEDIUM
Disclosed is a substrate processing apparatus including: a processing chamber that accommodates a substrate; a light source that radiates energy rays for a...
2018/0218928 METHODS AND APPARATUS FOR CORRECTING SUBSTRATE DEFORMITY
Embodiments of methods and apparatus for correcting substrate deformity are provided herein. In some embodiments, a substrate support includes a base having an...
2018/0218927 Substrate Processing Apparatus
Provided is a technique in which a heating-up time inside a process chamber is reduced. The technique includes a substrate processing apparatus including a...
2018/0218926 ACTIVE THERMAL CONTROL HEAD HAVING ACTUATABLE COLD CAPACITOR
A thermal control head for a semiconductor device handler includes: a heater configured to heat a semiconductor device; a cold manifold; and a cooling mass...
2018/0218925 HEATING APPARATUS AND SUBSTRATE PROCESSING APPARATUS
Time periods required for a wafer W to reach a reference temperature are made to be uniform between heating modules 2 and between heating target regions in a...
2018/0218924 SUBSTRATE LIQUID TREATMENT APPARATUS
A substrate liquid treatment apparatus includes an inner tank configured to store a treatment liquid and having an upper opening, an outer tank disposed...
2018/0218923 HOT VACUUM DRYING DEVICE APPLIED FOR FLEXIBLE SUBSTRATE
The present invention provides a hot vacuum drying device applied for a flexible substrate. By respectively improving the first support pin (5) and the second...
2018/0218922 CONTROL OF UNDER-FILL WITH A PACKAGING SUBSTRATE HAVING AN INTEGRATED TRENCH FOR A DUAL-SIDED BALL GRID ARRAY...
Described herein are methods of manufacturing dual-sided packaged electronic modules to control the distribution of an under-fill material between one or more...
2018/0218921 SEMICONDUCTOR CHIP
A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and...
2018/0218920 GRAPHITE HEAT SINK
A graphite heat sink that is light in weight, excellent in thermal conductivity and high in mechanical strength. A graphite heat sink includes two or more...
2018/0218919 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for...
2018/0218918 CHEMICAL MECHANICAL POLISHING METHOD FOR TUNGSTEN USING POLYGLYCOLS AND POLYGLYCOL DERIVATIVES
A process for chemical mechanical polishing a substrate containing tungsten is disclosed to reduce corrosion rate and inhibit dishing of the tungsten and...
2018/0218917 METHOD OF PATTERNING SEMICONDUCTOR DEVICE
A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the...
2018/0218916 SURFACE MACHINING METHOD FOR SINGLE CRYSTAL SIC SUBSTRATE, MANUFACTURING METHOD THEREOF, AND GRINDING PLATE FOR...
A surface machining method for a single crystal SiC substrate, including: a step of mounting a grinding plate which includes a soft pad and a hard pad...
2018/0218915 ISOTROPIC ETCHING OF FILM WITH ATOMIC LAYER CONTROL
A method for isotropically etching film on a substrate with atomic layer control includes a) providing a substrate including a material selected from a group...
2018/0218913 SALICIDE BOTTOM CONTACTS
A method of forming a contact to a semiconductor device that includes forming a vertically orientated channel region on semiconductor material layer of a...
2018/0218912 Pre-Deposition Treatment and Atomic Layer Deposition (ALD) Process and Structures Formed Thereby
Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A...
2018/0218911 MODIFYING WORK FUNCTION OF A METAL FILM WITH A PLASMA PROCESS
A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential...
2018/0218910 SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate; a p-type GaN layer that is formed above the substrate, and includes GaN containing p-type impurities; and a Ti...
2018/0218909 PLASMA SHALLOW DOPING AND WET REMOVAL OF DEPTH CONTROL CAP
A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a...
2018/0218908 PLASMA SHALLOW DOPING AND WET REMOVAL OF DEPTH CONTROL CAP
A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a...
2018/0218907 PLASMA SHALLOW DOPING AND WET REMOVAL OF DEPTH CONTROL CAP
A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a...
2018/0218906 METHOD OF MAKING A SEMICONDUCTOR SWITCH DEVICE
A method of making a semiconductor switch device. The method includes providing a semiconductor substrate having a major surface and a first semiconductor...
2018/0218905 APPLYING EQUALIZED PLASMA COUPLING DESIGN FOR MURA FREE SUSCEPTOR
A method and apparatus for equalized plasma coupling is provided herein. Discontinuity marks, also known as golf tee mura, are eliminated or minimized by...
2018/0218904 Method of Forming an Integrated Circuit
A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of...
2018/0218903 Charged-Particle-Beam Patterning Without Resist
A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of...
2018/0218902 BORON DOPED TUNGSTEN CARBIDE FOR HARDMASK APPLICATIONS
Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein...
2018/0218901 MANUFACTURING OF FOREIGN OXIDE OF FOREIGN NITRIDE ON SEMICONDUCTOR
A method for forming a foreign oxide or foreign nitride layer (6) on a substrate (1) of a semiconductor comprises providing a semiconductor substrate (1)...
2018/0218900 SELECTIVE EPITAXY USING EPITAXY-PREVENTION LAYERS
A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the...
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