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Patent # Description
2018/0226453 SCALABLE, STACKABLE, AND BEOL-PROCESS COMPATIBLE INTEGRATED NEURON CIRCUIT
An integrated neuron circuit structure comprising at least one thin-film resistor, one Metal Insulator Metal capacitor and one Negative Differential Resistance...
2018/0226452 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element. The variable resistance...
2018/0226451 ADVANCED PROCESSING APPARATUS COMPRISING A PLURALITY OF QUANTUM PROCESSING ELEMENTS
The present disclosure provides a scalable architecture for an advanced processing apparatus for performing quantum processing. The architecture is based on an...
2018/0226450 LIGHT EMITTING UNIT AND DISPLAY DEVICE
A light emitting unit has a first electrode, a second electrode and an epitaxial structure disposed between the first electrode and the second electrode. The...
2018/0226449 3DIC Interconnect Apparatus and Method
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are...
2018/0226448 EDGE REFLECTION REDUCTION
A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a first...
2018/0226447 EDGE REFLECTION REDUCTION
A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a...
2018/0226446 SOLID-STATE IMAGING APPARATUS AND METHOD OF MANUFACTURING THE SAME
A solid-state imaging apparatus includes: an imaging section having a light-receiving portion for receiving light from an object to image the object; and a...
2018/0226445 METHODS FOR HIGH-DYNAMIC-RANGE COLOR IMAGING
A method for manufacturing a high-dynamic-range color image sensor includes (a) depositing a color filter layer on a silicon substrate having a photosensitive...
2018/0226444 SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS
A solid-state imaging device according to the present disclosure includes: a semiconductor base; a photoelectric conversion element provided in the...
2018/0226443 OPTICAL MODULES INCLUDING CUSTOMIZABLE SPACERS FOR FOCAL LENGTH ADJUSTMENT AND/OR REDUCTION OF TILT, AND...
An optical module comprising: a plurality of active optoelectronic components each one mounted on a respective printed circuit board (PCB), wherein each active...
2018/0226442 IMAGE SENSOR AND MANUFACTURING METHOD THEREOF
An image sensor including a device chip, a plurality of spacers, a dam layer, a lid, and a plurality of conductive terminals. The device chip has a first...
2018/0226441 SOLID STATE IMAGING DEVICE
A solid-state imaging device includes a first semiconductor substrate including a pixel array unit, a second semiconductor substrate stacked on a surface of a...
2018/0226440 IMAGE SENSOR AND METHOD FOR FORMING THE SAME
An image sensor and a method for forming an image sensor are provided. The image sensor includes a substrate, and the substrate includes a pixel region, a...
2018/0226439 SOLID-STATE IMAGING DEVICE
A plurality of pixels are two-dimensionally arranged on a semiconductor substrate. Each of the pixels includes: two photodiodes each generating charge by...
2018/0226438 TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is...
2018/0226437 DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE
A display substrate, a manufacturing method thereof and a display device are provided. The manufacturing method of the display substrate includes: forming a...
2018/0226436 THIN-FILM TRANSISTOR ARRAY SUBSTRATE WITH CONNECTION NODE AND DISPLAY DEVICE INCLUDING THE SAME
A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a...
2018/0226435 METHOD FOR FORMING SEMICONDUCTOR DEVICE
The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After...
2018/0226434 DISPLAY DEVICE
A pixel portion and a driver circuit driving the pixel portion are formed over the same substrate. At least a part of the driver circuit is formed using an...
2018/0226433 DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE
A display device includes a common electrode provided to cross over the boundary between a display region and a non-display region. The common electrode is a...
2018/0226432 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are...
2018/0226431 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Reliability of a semiconductor device is improved. Prepared is a substrate in which an insulating layer, a semiconductor layer, and an insulating film are...
2018/0226430 DISPLAY DEVICE
Disclosed is a display device including: a substrate including a display area for displaying an image and a peripheral area neighboring the display area; a...
2018/0226429 DISPLAY PANEL AND DISPLAY DEVICE
Disclosed are a display panel and a display device. The display panel includes: a first substrate and a second substrate disposed as opposed to each other. The...
2018/0226428 Memory Cells Comprising A Programmable Field Effect Transistor Having A Reversibly Programmable Gate Insulator
A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two...
2018/0226427 Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material...
Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower...
2018/0226426 ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES
Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and...
2018/0226425 ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES
Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and...
2018/0226424 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH INCLINED GATE ELECTRODES
A three-dimensional semiconductor device includes a substrate including a cell array region and a contact region, a stack structure including gate electrodes...
2018/0226423 INTEGRATED CIRCUIT DEVICE INCLUDING VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the...
2018/0226422 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor memory device according to an embodiment includes a stacked body in which an electrode film and an insulating film are alternately stacked...
2018/0226421 METHOD OF FORMING SPLIT-GATE, TWIN-BIT NON-VOLATILE MEMORY CELL
A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and...
2018/0226420 Split Gate Non-volatile Flash Memory Cell Having Metal Gates
A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area....
2018/0226419 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor...
2018/0226418 CAPACITOR COMPRISING A BISMUTH METAL OXIDE-BASED LEAD TITANATE THIN FILM
In some examples, a system comprises a capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and the...
2018/0226417 STRUCTURE FEATURING FERROELECTRIC CAPACITANCE IN INTERCONNECT LEVEL FOR STEEP SUB-THRESHOLD COMPLEMENTARY METAL...
After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate...
2018/0226416 STRUCTURE FEATURING FERROELECTRIC CAPACITANCE IN INTERCONNECT LEVEL FOR STEEP SUB-THRESHOLD COMPLEMENTARY METAL...
After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate...
2018/0226415 STRUCTURE FEATURING FERROELECTRIC CAPACITANCE IN INTERCONNECT LEVEL FOR STEEP SUB-THRESHOLD COMPLEMENTARY METAL...
After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate...
2018/0226414 Three-Dimensional Vertical One-Time-Programmable Memory Comprising Schottky Diodes
The present invention discloses a three-dimensional vertical read-only memory (3D-OTP.sub.V) comprising Schottky diodes. It comprises a plurality of vertical...
2018/0226413 SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE
A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the...
2018/0226412 Three-Dimensional Static Random Access Memory Device Structures
Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM...
2018/0226411 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region,...
2018/0226410 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping...
2018/0226409 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line...
2018/0226408 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a...
2018/0226407 FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
2018/0226406 APPARATUSES INCLUDING BURIED DIGIT LINES
Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material...
2018/0226405 LOW DAMAGE SELF-ALIGNED AMPHOTERIC FINFET TIP DOPING
Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor....
2018/0226404 SEMICONDUCTOR DEVICE
A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns;...
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