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Patent # Description
2018/0226352 METHOD TO REDUCE VARIABILITY IN CONTACT RESISTANCE
Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce...
2018/0226351 FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first...
2018/0226350 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface...
2018/0226349 Multi-Stacked Package-on-Package Structures
A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the...
2018/0226348 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device package includes a flexible substrate, an electronic component, at least one flexible member, and a package body. The electronic...
2018/0226347 Heterojunction Bipolar Transistors With Stress Material For Improved Mobility
According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a...
2018/0226346 THIN FILM ELEMENT AND METHOD FOR MANUFACTURING THE SAME
A thin film element that includes a base material, a wiring conductor film disposed on the surface of the base material, a protective film that covers the...
2018/0226345 FUSE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. The...
2018/0226344 FUSE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. The...
2018/0226343 FABRICATION OF VERTICAL FUSES FROM VERTICAL FINS
A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction...
2018/0226342 Bonding Structures and Methods Forming the Same
A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the...
2018/0226341 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device according to the present embodiment includes a stacked body having an end which is step-shaped and a contact in each of the steps of the...
2018/0226340 SERIES MIM STRUCTURES
The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip...
2018/0226339 THREE PLATE MIM CAPACITOR VIA INTEGRITY VERIFICATION
A three plate MIM capacitor structure includes a three plate MIM capacitor, a first wire in a metal layer above/below the three plate MIM, a second wire...
2018/0226338 THREE PLATE MIM CAPACITOR VIA INTEGRITY VERIFICATION
A three plate MIM capacitor test structure includes a three plate MIM capacitor, a first test wire in a metal layer above/below the three plate MIM, a second...
2018/0226337 Multiple Metal Layer Semiconductor Device and Low Temperature Stacking Method of Fabricating the Same
A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first...
2018/0226336 INTEGRATED CIRCUIT INCLUDING STANDARD CELL
An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail...
2018/0226335 SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit includes an output circuit connected between a power supply and a node at which a load can be connected. The output circuit...
2018/0226334 MULTI-DIE PACKAGE
Embodiments herein may relate to a package that includes a package substrate with a first die on a first side of the package substrate and a second die on a...
2018/0226333 SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound,...
2018/0226332 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure includes an interconnection layer; a passivation layer disposed on the interconnection layer, in which the interconnection layer and the...
2018/0226331 GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES
Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are...
2018/0226330 ALTERNATIVE SURFACES FOR CONDUCTIVE PAD LAYERS OF SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are...
2018/0226329 METHOD OF FORMING SEMICONDUCTOR STRUCTURE
A method of forming a semiconductor device includes forming a first redistribution line on a substrate; forming a plurality of first vertical conductive...
2018/0226328 COAXIAL VIAS
Embodiments herein may relate to a substrate that includes a coaxial via with a signal portion and a ground shield portion. In embodiments, the via may further...
2018/0226327 LEAD FRAME AND METHOD FOR MANUFACTURING THE SAME
A lead frame constitutes a product unit in a multi-row lead frame and has a dam bar and a lead connected together. The dam bar has a first site where...
2018/0226326 ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS
An electro-optical device includes a first drive IC and a second drive IC which are respectively mounted on a first flexible wiring substrate and a second...
2018/0226325 Integrated Circuit (IC) Package with a Solder Receiving Area and Associated Methods
A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the...
2018/0226324 SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONVERSION DEVICE
A semiconductor device includes: a base plate including a metallic base plate and an insulating film provided on the metallic base plate; a semiconductor chip...
2018/0226323 INTEGRATED CIRCUIT HAVING CONTACT JUMPER
An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially...
2018/0226322 THERMOELECTRIC BONDING FOR INTEGRATED CIRCUITS
Techniques for thermal management of an integrated circuit die are provided. In an example, an apparatus can include a first integrated circuit die having a...
2018/0226321 SEMICONDUCTOR STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon;...
2018/0226320 SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second...
2018/0226319 VEHICLE CONTROL DEVICE
A vehicle control device (100) includes: a housing (200) made of metal; a substrate (400) housed in the housing (200) and having a mounting surface (401) that...
2018/0226318 POWER ELECTRONICS MODULE
A power electronics module and a method of manufacturing a power electronics module and a base plate. The power electronics module comprising at least one...
2018/0226317 NON-PLANAR ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES WITH NANO HEAT SINKS
The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by...
2018/0226316 Circuit Package
A circuit package comprises a circuit device in a first epoxy mold compound and a second epoxy mold compound of different compositions.
2018/0226315 ELECTRONIC SWITCHING ELEMENT AND MODULARLY CONSTRUCTED POWER CONVERTER
An electronic switching element includes at least one semiconductor switch inserted into a layer sequence of a conductor structure element; and at least two...
2018/0226314 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second...
2018/0226313 FORMULATIONS CONTAINING MIXED RESIN SYSTEMS AND THE USE THEREOF FOR WAFER-LEVEL UNDERFILL FOR 3D TSV PACKAGES
Provided herein are mixed resin systems and the use thereof for wafer-level underfill (WAUF) for three-dimensional TSV packages. In one aspect, there are...
2018/0226312 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a manufacturing method thereof, which can reduce the size of the semiconductor package and improve product reliability. In a...
2018/0226311 SUPPORTING GLASS SUBSTRATE, LAMINATE, SEMICONDUCTOR PACKAGE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING...
Devised are a supporting substrate capable of contributing to an increase in density of a semiconductor package and a laminate using the supporting substrate....
2018/0226310 PACKAGE-INTEGRATED MICROCHANNELS
Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package...
2018/0226309 WAFER LEVEL PACKAGE SOLDER BARRIER USED AS VACUUM GETTER
An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the...
2018/0226308 TIME TEMPERATURE MONITORING SYSTEM
A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active...
2018/0226307 SYSTEM AND METHOD FOR ELECTRICAL TESTING OF THROUGH SILICON VIAS (TSVs)
A substrate includes first and second semiconductor layers doped with opposite conductivity type in contact with each other at a PN junction to form a junction...
2018/0226306 METHOD FOR PECVD OVERLAY IMPROVEMENT
The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic...
2018/0226305 SYSTEM AND METHOD FOR MEASUREMENT OF COMPLEX STRUCTURES
A system and method of use for simplifying the measurement of various properties of complex semiconductor structures is provided. The system and method...
2018/0226304 System and Method for Measuring Substrate and Film Thickness Distribution
The system includes a dual interferometer sub-system configured to measure flatness across a substrate. The system includes a mass sensor configured to measure...
2018/0226303 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming transistors in a cell region of a test wafer, forming a first test pattern on a first test...
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