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Patent # Description
2018/0226302 TFT BACKPLANE MANUFACTURING METHOD AND TFT BACKPLANE
The invention provides a manufacturing method for TFT backplane, through forming an oxygen-containing a-Si layer on the buffer layer and an oxygen-free a-Si...
2018/0226301 Method and Apparatus with Channel Stop Doped Devices
Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface...
2018/0226299 SHALLOW TRENCH ISOLATION STRUCTURES AND CONTACT PATTERNING
A dual layer shallow isolation trench region for semiconductor structures including field effect transistors (FETs) and methods for making the same. The first...
2018/0226298 SHALLOW TRENCH ISOLATION STRUCTURES AND CONTACT PATTERNING
A dual layer shallow isolation trench region for semiconductor structures including field effect transistors (FETs) and methods for making the same. The first...
2018/0226297 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds...
2018/0226296 WIMPY DEVICE BY SELECTIVE LASER ANNEALING
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form...
2018/0226295 PROCESSING METHOD OF WAFER
A processing method of a wafer includes a cut groove forming step of carrying out cutting with a cutting blade along streets from the back surface of the wafer...
2018/0226294 DEVICES WITH CHAMFER-LESS VIAS MULTI-PATTERNING AND METHODS FOR FORMING CHAMFER-LESS VIAS
Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for...
2018/0226293 Porogen Bonded Gap Filling Material in Semiconductor Manufacturing
A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and...
2018/0226292 TRENCH ISOLATION FORMATION FROM THE SUBSTRATE BACK SIDE USING LAYER TRANSFER
Structures with trench isolation and methods for making a structure with trench isolation. A transistor is formed by front-end-of-line processing on a first...
2018/0226291 Integrated Bi-Layer STI Deposition
A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into...
2018/0226290 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the...
2018/0226289 ULTRA THIN HELMET DIELECTRIC LAYER FOR MASKLESS AIR GAP AND REPLACEMENT ILD PROCESSES
A helmet layer is deposited on a plurality of conductive features on a first dielectric layer on a substrate. A second dielectric layer is deposited on a first...
2018/0226288 MULTIPLE-STAGE PROCESSING DEVICES
A multiple stage processing device having a plurality of radial stages, each individual radial stage is positioned between adjacent dividing walls and...
2018/0226287 MICRO-TRANSFER-PRINTABLE FLIP-CHIP STRUCTURES AND METHODS
In certain embodiments, a method of making a semiconductor structure suitable for transfer printing (e.g., micro-transfer printing) includes providing a...
2018/0226286 CARRIER SUBSTRATE FOR CARRYING AN OLED IN MANUFACTURING PROCESS AND MANUFACTURING METHOD FOR THE SAME
A carrier substrate for carrying an OLED in manufacturing process is disclosed. The carrier substrate includes a substrate and an attracted layer disposed on a...
2018/0226285 HEATER UNIT
A heater unit having high in-plane temperature uniformity is provided. A heater unit includes a first heater part, a second heater part controlled ...
2018/0226284 SYSTEMS, APPARATUS, AND METHODS FOR A LOAD PORT DOOR OPENER
Embodiments provide systems, apparatus, and methods for an improved load port operable to purge air trapped between the substrate carrier door and the carrier...
2018/0226283 METHOD SYSTEM FOR GENERATING 3D COMPOSITE IMAGES OF OBJECTS AND DETERMINING OBJECT PROPERTIES BASED THEREON
A 3D object inspection process includes: capturing an object bottom surface 3D profile (a) while an object top surface freely rests on an object seating...
2018/0226282 NON-CONTACT SUBSTRATE TEMPERATURE MEASUREMENT TECHNIQUE BASED ON SPECTRAL INTEFEROMETRY
In some embodiments, an apparatus for processing substrates includes: a substrate support within a processing chamber; a light source directly coupled to a...
2018/0226281 PICKUP APPARATUS
According to one embodiment, a pickup apparatus picks up one of a plurality of semiconductor chips from a sheet. The plurality of semiconductor chips is...
2018/0226280 LOAD LOCK FAST PUMP VENT
A semiconductor processing tool is disclosed, the tool having a frame forming at least one chamber with an opening and having a sealing surface around a...
2018/0226279 PLASMA PROCESSING METHOD
A plasma processing method of processing a processing target object, in which an organic film, a mask film and a resist film are stacked in sequence, by plasma...
2018/0226278 SELF-LIMITING ATOMIC THERMAL ETCHING SYSTEMS AND METHODS
Systems and methods of etching a semiconductor substrate may include flowing an oxygen-containing precursor into a substrate processing region of a...
2018/0226277 LIQUID PROCESSING APPARATUS
A liquid processing apparatus according to an embodiment includes a holding unit, a driving unit, a shaft, and a nozzle. The driving unit rotates the substrate...
2018/0226276 Method for Fabricating a Semiconductor Chip Panel
A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a plurality of semiconductor chips, wherein each...
2018/0226275 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The reliability of a semiconductor device is improved. During resin injection in a molding step, in a plan view, a plurality of gates of a molding die are arranged...
2018/0226274 CONTROL OF UNDER-FILL USING AN ENCAPSULANT FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE
Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use an encapsulant on solder balls to control the...
2018/0226273 CONTROL OF UNDER-FILL USING A DAM ON A PACKAGING SUBSTRATE FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE
Described herein are methods of manufacturing dual-sided packaged electronic modules to control the distribution of an under-fill material between one or more...
2018/0226272 CONTROL OF UNDER-FILL USING UNDER-FILL DEFLASH FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE
Described herein methods of manufacturing dual-sided packaged electronic modules that control the distribution of an under-fill material between one or more...
2018/0226271 CONTROL OF UNDER-FILL USING A FILM DURING FABRICATION FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE
Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use a film during fabrication to control the...
2018/0226270 METHOD FOR FABRICATING MACH-ZEHNDER MODULATOR, MACH-ZEHNDER MODULATOR
A method for fabricating a Mach-Zehnder modulator includes: forming a resin body embedding a semiconductor mesa for an arm waveguide, the resin body having an...
2018/0226269 METHOD FOR ROUGHENING THE SURFACE OF A METAL LAYER, THIN FILM TRANSISTOR, AND METHOD FOR FABRICATING THE SAME
The disclosure discloses a method for roughening a surface of a metal layer, a thin film transistor, and a method for fabricating the same. The method for...
2018/0226268 SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor manufacturing apparatus according to the present embodiment has a mount unit capable of mounting a substrate. A first supplier supplies a...
2018/0226267 SEMICONDUCTOR TREATMENT COMPOSITION AND TREATMENT METHOD
A semiconductor treatment composition includes potassium, sodium, and a compound A represented by the formula (1), and has a potassium content M.sub.K (ppm)...
2018/0226266 ACTIVE MATRIX SUBSTRATE
An active matrix substrate includes a substrate 31; gate lines arranged on the substrate 31 and extend in a first direction; source lines Si arranged on the...
2018/0226265 Critical Dimension Control for Double Patterning Process
In a method for manufacturing a semiconductor device, a dummy gate layer and a hard mask layer are sequentially formed on a substrate. A first doped portion is...
2018/0226264 PLASMA ETCHING METHOD
A plasma etching method includes a first process of generating a first plasma from a first processing gas that contains fluorine-containing gas and...
2018/0226263 METHOD AND APPARATUS FOR WITHIN-WAFER PROFILE LOCALIZED TUNING
A method and apparatus for within-wafer profile localized tuning is disclosed. In one aspect, the method includes providing a wafer attached to a rotating...
2018/0226262 MARGIN FOR FIN CUT USING SELF-ALIGNED TRIPLE PATTERNING
A method for fabricating a semiconductor structure. The method includes forming a plurality of mandrel structures. A plurality of first spacers is formed on...
2018/0226261 METHOD OF ANISOTROPICALLY ETCHING GRAPHENE
A method for anisotropically etching graphene includes generating hydrogen plasma by microwave plasma, and anisotropically etching graphene by the generated...
2018/0226260 DIELECTRIC CONTACT ETCH
A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and...
2018/0226259 Shaped Etch Profile with Oxidation
Processing methods may be performed to form recesses in a semiconductor substrate. The methods may include oxidizing an exposed silicon surface on a...
2018/0226258 METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER
A method for manufacturing a semiconductor wafer including: slicing off a plurality of wafers from an ingot; chamfering outer peripheral portions of the...
2018/0226257 DEVICES WITH MULTIPLE THRESHOLD VOLTAGES FORMED ON A SINGLE WAFER USING STRAIN IN THE HIGH-K LAYER
A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a...
2018/0226256 THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, AND DISPLAY DEVICE
Disclosed are a thin film transistor, a method for fabricating the same, and a display device, where the fabricating method includes: forming a gate insulation...
2018/0226255 MICROWAVE PLASMA DEVICE
A processing system is disclosed, having a power transmission element with an interior cavity that propagates electromagnetic energy proximate to a continuous...
2018/0226254 Systems and Methods for Bidirectional Device Fabrication
Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a ...
2018/0226253 SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A substrate for semiconductor device includes a substrate, a reaction layer provided on a back surface of the substrate, a transmission preventing metal having...
2018/0226252 Method for Planarizing Graphene Layer
There is provided a method for planarizing irregularities in a surface of a grapheme layer formed on a substrate, including: planarizing the grapheme layer by...
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