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Patent # Description
2018/0233516 CMOS With Middle Of Line Processing Of III-V Material On Mandrel
A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming...
2018/0233515 MANUFACTURING METHOD OF DISPLAY SUBSTRATE, DISPLAY SUBSTRATE AND DISPLAY DEVICE
A manufacturing method of a display substrate, a display substrate and a display device are provided. The manufacturing method of a display substrate...
2018/0233514 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure relates to a semiconductor structure. The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate having a bottom...
2018/0233513 THREE-DIMENSIONAL NAND MEMORY DEVICE WITH COMMON BIT LINE FOR MULTIPLE NAND STRINGS IN EACH MEMORY BLOCK
A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating...
2018/0233512 THREE-DIMENSIONAL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING REPLACEMENT GATE
The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical...
2018/0233511 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME
An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor...
2018/0233510 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a...
2018/0233509 STRAP LAYOUT FOR NON-VOLATILE MEMORY DEVICE
A device and methods for forming the device are disclosed. The method includes providing a substrate prepared with a memory cell region and forming memory cell...
2018/0233508 READ-ONLY MEMORY (ROM) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A read-only memory (ROM) structure is provided. The ROM device structure includes a first gate structure formed over a substrate, and the first gate structure...
2018/0233507 SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES
A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a...
2018/0233506 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a...
2018/0233505 SELF-ALIGNED SACRIFICIAL EPITAXIAL CAPPING FOR TRENCH SILICIDE
A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in...
2018/0233504 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a...
2018/0233503 TIGHT PITCH INVERTER USING VERTICAL TRANSISTORS
CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the...
2018/0233502 VERTICAL TRANSISTOR TRANSMISSION GATE WITH ADJACENT NFET AND PFET
A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs)...
2018/0233501 VERTICAL TRANSISTOR TRANSMISSION GATE WITH ADJACENT NFET AND PFET
A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs)...
2018/0233500 FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS WITH UNIFORM STRUCTURAL PROFILES
Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods...
2018/0233499 IMPEDANCE CIRCUIT WITH POLY-RESISTOR
An impedance circuit includes a first poly-resistor and a second poly-resistor. The first poly-resistor has a first terminal coupled to a first node, and a...
2018/0233498 SUBSTRATE AND DISPLAY DEVICE CONTAINING THE SAME
The present disclosure provides a substrate, including: a first line; a second line; a thin-film transistor (TFT) between the first line and the second line,...
2018/0233497 SEMICONDUCTOR DEVICE
A semiconductor device used in a protection circuit including a thyristor and an LCR circuit which includes a coil L, a capacitor C and a resistor R, the...
2018/0233496 MICRO-LED MODULE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a micro-LED module is disclosed. The method includes: preparing a micro-LED including a plurality of electrode pads and a plurality of...
2018/0233495 SUBSTRATE WITH ARRAY OF LEDS FOR BACKLIGHTING A DISPLAY DEVICE
An apparatus includes a substrate and a circuit trace having a predetermined pattern disposed on the substrate. A plurality of LEDs are connected to the...
2018/0233494 DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
A display apparatus and a method of manufacturing the same. The display apparatus includes a circuit board; and a plurality of pixels formed on the circuit...
2018/0233493 LIGHT EMITTING DEVICE, BACKLIGHT DEVICE, AND MANUFACTURING METHOD OF LIGHT EMITTING DEVICE
In order to be more compact and thin, this light emitting device includes LED elements embedded in a resin molded body such that light emitting units are...
2018/0233492 TRIANGULAR-COMBINATION LED CIRCUIT BOARD, TRIANGULAR LED DEVICE AND DISPLAY
A triangular-combination LED circuit board, comprising a plurality of triangular LED units, wherein vertexes of every six of the LED units are superimposed to...
2018/0233491 SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES
A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the...
2018/0233490 SEAL-RING STRUCTURE FOR STACKING INTEGRATED CIRCUITS
A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first...
2018/0233489 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and...
2018/0233488 INTEGRATED CIRCUIT PACKAGE WITH THERMALLY CONDUCTIVE PILLAR
Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally...
2018/0233487 Dual-Chip Package Structure
A dual-chip package structure is provided with an exposed pad as a ground terminal for being electrically coupled to GND bonding pads of two chips in the...
2018/0233486 DIE DEVICE, SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the...
2018/0233485 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate including a conductive pillar protruded from the substrate; and a first chip disposed over the substrate and...
2018/0233484 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a first die; a second die disposed over or at least partially in contact with the first die; a redistribution layer (RDL)...
2018/0233483 GALLIUM LIQUID METAL EMBRITTLEMENT FOR DEVICE REWORK
A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes...
2018/0233482 GALLIUM LIQUID METAL EMBRITTLEMENT FOR DEVICE REWORK
A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes...
2018/0233481 HIGH VOLTAGE DEVICE WITH MULTI-ELECTRODE CONTROL
A high-voltage transistor (HVT) structure adapts a low-voltage transistor (LUT) to high-voltage environments. The HVT structure includes a drain node, a source...
2018/0233480 SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME
The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a...
2018/0233479 SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME
The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a...
2018/0233478 METHOD OF FABRICATING PACKAGING STRUCTURE
A package structure includes a dielectric layer having opposing first and second surfaces, a wiring layer formed on the first surface and having a plurality of...
2018/0233477 ELECTRONIC PACKAGING STRUCTURE
An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an...
2018/0233476 SEMICONDUCTOR PACKAGE
The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface...
2018/0233475 SEMICONDUCTOR DEVICE
A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically...
2018/0233474 SEMICONDUCTOR PACKAGE WITH RIGID UNDER BUMP METALLURGY (UBM) STACK
The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive...
2018/0233473 PASTE THERMOSETTING RESIN COMPOSITION, SEMICONDUCTOR COMPONENT, SEMICONDUCTOR MOUNTED ARTICLE, METHOD FOR...
Provided is a paste thermosetting resin composition containing solder powder, a thermosetting resin binder, an activator, and a thixotropy imparting agent. The...
2018/0233472 MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top...
2018/0233471 Filter and Capacitor Using Redistribution Layer and Micro Bump Layer
An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above...
2018/0233470 HANDLING THIN WAFER DURING CHIP MANUFACTURE
A manufacturing method is provided which comprises forming recesses in a front side of a wafer, connecting a first temporary holding body to the front side of...
2018/0233469 DEVICE INCLUDING SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING SUCH DEVICE
A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a...
2018/0233468 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a...
2018/0233467 Method for Building up a Fan-Out RDL Structure with Fine Pitch Line-Width and Line-Spacing
A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface...
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