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Patent # Description
2018/0233466 SEMICONDUCTOR DEVICE WITH CONTACT PAD AND FABRICATION METHOD THEREFORE
A method of fabricating a semiconductor structure includes forming a conductive structure over a first passivation layer, depositing a first dielectric film...
2018/0233465 INTEGRATED CIRCUIT PACKAGE
An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a...
2018/0233464 SEMICONDUCTOR MODULE
A semiconductor modules includes insulating substrates having first and second patterns thereon. One terminal plate connects the first patterns and another...
2018/0233463 GROUNDING TECHNIQUES FOR BACKSIDE-BIASED SEMICONDUCTOR DICE AND RELATED DEVICES, SYSTEMS AND METHODS
Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased...
2018/0233462 SEAL RING FOR WAFER LEVEL PACKAGE
Devices and methods for forming a device are disclosed. At least one die is provided. A redistribution layer having a fan-out region extends concentrically...
2018/0233461 SEMICONDUCTOR DEVICE AND AUTHENTICATION SYSTEM
In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in...
2018/0233460 DECOUPLING CAPACITOR
A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without...
2018/0233459 MODULE, MODULE MANUFACTURING METHOD, AND PACKAGE
A first substrate, a second substrate, and a retaining member are included. On the first substrate, a heat-generating part is mounted. The second substrate is...
2018/0233458 INTEGRATED CIRCUIT PACKAGE
An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit...
2018/0233457 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic...
2018/0233455 SEMICONDUCTOR PROCESSING METHOD
A semiconductor processing method is provided. The method includes providing a first carrier (10). A first adhesive (18) is provided on the first carrier (10)...
2018/0233454 FAN-OUT SEMICONDUCTOR PACKAGE
The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a...
2018/0233453 INPUT/OUTPUT PINS FOR CHIP-EMBEDDED SUBSTRATE
Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed...
2018/0233452 SEMICONDUCTOR PACKAGE ASSEMBLY
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor...
2018/0233451 PAD STRUCTURE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a pad structure includes the steps of: providing a material layer; forming an opening in the material layer; forming a conductive...
2018/0233450 Methods of Manufacturing Semiconductor Devices
The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device...
2018/0233449 METHOD FOR FABRICATING CONTACT ELECTRICAL FUSE
A method for fabricating semiconductor device includes the steps of first forming a first dielectric layer on a substrate, in which a first conductor is...
2018/0233448 Substrate-Less Stackable Package With Wire-Bond Interconnect
A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a...
2018/0233447 MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM...
In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A,...
2018/0233446 INTEGRATING METAL-INSULATOR-METAL CAPACITORS WITH AIR GAP PROCESS FLOW
Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect...
2018/0233445 LOW RESISTANCE SEED ENHANCEMENT SPACERS FOR VOIDLESS INTERCONNECT STRUCTURES
An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier...
2018/0233444 LOW RESISTANCE SEED ENHANCEMENT SPACERS FOR VOIDLESS INTERCONNECT STRUCTURES
An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier...
2018/0233443 SEMICONDUCTOR PACKAGES
A semiconductor package includes: a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining...
2018/0233442 FABRICATION METHOD OF LAYER STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE
A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the...
2018/0233441 PoP Device
A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the...
2018/0233440 RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE
A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed...
2018/0233439 SEMICONDUCTOR CHIP PACKAGE HAVING HEAT DISSIPATING STRUCTURE
Disclosed herein is a semiconductor chip package having a heat dissipating structure. The semiconductor chip package including: a semiconductor chip configured...
2018/0233438 LEADFRAME, SEMICONDUCTOR PACKAGE INCLUDING A LEADFRAME AND METHOD FOR FORMING A SEMICONDUCTOR PACKAGE
A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality...
2018/0233437 SEMICONDUCTOR DEVICE
A semiconductor device comprises a plurality of first conductor portions 10, a plurality of second conductor portions 20 and a sealing portion 50, covering...
2018/0233436 CHIP-ON-FILM PACKAGE, DISPLAY PANEL, AND DISPLAY DEVICE
A chip-on-film package includes a base substrate on which a first pad region, a second pad region, and a third region located between the first pad region and...
2018/0233435 SEMICONDUCTOR DEVICE
A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode,...
2018/0233434 SEMICONDUCTOR DEVICE
A first diode having a front surface anode region is mounted on a P pattern, and a second diode having a front surface cathode region is mounted on an N...
2018/0233433 FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A fan-out semiconductor package includes a semiconductor chip including a body and an electrode pad disposed on the body, a metal layer disposed on the...
2018/0233432 ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME
An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first...
2018/0233431 LITHOGRAPHACALLY DEFINED VIAS FOR ORGANIC PACKAGE SUBSTRATE SCALING
Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first...
2018/0233430 PROCESSING DEVICE AND PROCESSING SYSTEM
The present invention addresses the problem of reducing the number of terminals of a processing device while achieving both communication with another device...
2018/0233429 MULTILAYER BOARD AND ELECTRONIC DEVICE
A multilayer board includes a base including insulating layers stacked in a stacking direction, and a mounting surface at an end of the base in a first...
2018/0233428 HEAT DISSIPATION ASSEMBLY
A heat dissipation assembly capable of quickly dissipating heat emitted by a heating source of an electronic communication apparatus. The heat dissipation...
2018/0233427 GRAPHITE HEAT SINK
A graphite heat sink includes a graphite heat conductive plate and a heat radiation layer. One side of the graphite heat conductive plate is used for absorbing...
2018/0233426 Chip scale package
The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package...
2018/0233425 SEMICONDUCTOR PACKAGE WITH EMBEDDED SUPPORTER AND METHOD FOR FABRICATING THE SAME
The invention provides a semiconductor package and a method for fabricating the same. The semiconductor package includes a redistribution layer (RDL)...
2018/0233424 SEMICONDUCTOR PACKAGE DEVICE
A semiconductor package device includes a lead frame including a lead frame pad and lead frame leads, a semiconductor chip located on the lead frame pad, and a...
2018/0233423 FLIP-CHIP MOUNTING OF SILICON-ON-INSULATOR DIE
A component of an electronic device comprises a semiconductor die flip-chip mounted on a printed circuit board and a barrier mechanically coupled to a portion...
2018/0233422 SEMICONDUCTOR PACKAGE WITH A WIRE BOND MESH
A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically...
2018/0233421 Semiconductor Package, Assembly and Module Arrangements for Measuring Gate-to-Emitter/Source Voltage
One or more additional sense terminals are added to discrete semiconductor packages, assemblies and semiconductor modules, including power semiconductor...
2018/0233420 METHODS FOR ASSESSING SEMICONDUCTOR STRUCTURES
Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use...
2018/0233419 OVERLAY MARK AND METHOD FOR EVALUATING STABILITY OF SEMICONDUCTOR MANUFACTURING PROCESS
The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a...
2018/0233418 STRUCTURE AND METHOD FOR TENSILE AND COMPRESSIVE STRAINED SILICON GERMANIUM WITH SAME GERMANIUM CONCENTRATION...
A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion...
2018/0233417 DUAL LINER SILICIDE
A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate...
2018/0233416 METHOD FOR PREVENTING DISHING DURING THE MANUFACTURE OF SEMICONDUCTOR DEVICES
A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a...
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