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Patent # Description
2018/0233415 FINFET DEVICE AND METHOD OF MANUFACTURING
A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments...
2018/0233414 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH WIDER SIDEWALL SPACER FOR A HIGH VOLTAGE MISFET
An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The...
2018/0233413 GRAPHENE CONTACTS ON SOURCE/DRAIN REGIONS OF FINFET DEVICES
A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions...
2018/0233412 FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE
A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided....
2018/0233411 SEMICONDUCTOR DIE SINGULATION METHODS
Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first...
2018/0233410 WAFER DICING METHODS
Wafer dicing methods that simplify the singulation process for certain types of integrated circuit (IC) wafer substrates that improve device reliability and...
2018/0233409 TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE, AND ASSOCIATED CONFIGURATIONS
Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC...
2018/0233408 SELF ALIGNED CONDUCTIVE LINES WITH RELAXED OVERLAY
A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the...
2018/0233407 METHOD OF FORMING A SELF-ALIGNED CONTACT USING SELECTIVE SiO2 DEPOSITION
A substrate processing method for forming a self-aligned contact using selective SiO.sub.2 deposition is described in various embodiments. The method includes...
2018/0233406 Method of Semiconductor Integrated Circuit Fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on...
2018/0233405 SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating...
2018/0233404 VARIABLE SPACE MANDREL CUT FOR SELF ALIGNED DOUBLE PATTERNING
The present disclosure relates to semiconductor structures and, more particularly, to variable space mandrel cut for self-aligned double patterning and methods...
2018/0233403 SELF-ALIGNED QUADRUPLE PATTERNING (SAQP) FOR ROUTING LAYOUTS INCLUDING MULTI-TRACK JOGS
An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure...
2018/0233402 SEMICONDUCTOR DEVICE
An object of the present invention is to improve the operating characteristics of a semiconductor device. A semiconductor device has a contact plug that is formed...
2018/0233401 LOCAL TRAP-RICH ISOLATION
A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or...
2018/0233400 METHOD OF DEPOSITING CHARGE TRAPPING POLYCRYSTALLINE SILICON FILMS ON SILICON SUBSTRATES WITH CONTROLLABLE FILM...
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a...
2018/0233399 Devices with Backside Metal Structures and Methods of Formation Thereof
A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor...
2018/0233398 METHOD TO CREATE AIR GAPS
Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials,...
2018/0233397 Material-Handling Robot With Multiple End-Effectors
An apparatus including a robot drive having motors and coaxial drive shafts connected to the motors; and a robot arm connected to the robot drive. The robot...
2018/0233396 SUBSTRATE POSITION CALIBRATION FOR SUBSTRATE SUPPORTS IN SUBSTRATE PROCESSING SYSTEMS
Methods and apparatus for substrate position calibration for substrate supports in substrate processing systems are provided herein. In some embodiments, a...
2018/0233395 METHOD OF MANUFACTURING ELEMENT CHIP
A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to...
2018/0233394 METHOD FOR THE BONDING AND DEBONDING OF SUBSTRATES
A method for bonding a product substrate to a carrier substrate via a connection layer, wherein a soluble layer is applied between the connection layer and the...
2018/0233393 Methods for Controlling Clamping of Insulator-Type Substrate on Electrostatic-Type Substrate Support Structure
An insulator-type substrate is positioned on a support surface of a substrate support structure in exposure to a plasma. An initial clamping voltage is applied...
2018/0233392 SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE TRANSFER METHOD
There is provided a substrate processing system, including: a carrier transfer region in which a carrier that accommodates a substrate is transferred to a...
2018/0233391 RETRIEVING DEVICE AND STORING DEVICE
A retrieving device 1 includes: a supporting unit 13 configured to support a front portion of the load 120 from a front side of the load 120; a coupling unit...
2018/0233390 WAFER SUPPORT COLUMN WITH INTERLOCKING FEATURES
A substrate support assembly for a substrate container. The assembly may include a pair of substrate support columns each including a stack of a plurality of...
2018/0233389 ALIGNMENT METHOD, PATTERN FORMATION SYSTEM, AND EXPOSURE DEVICE
According to one embodiment, an alignment method includes calculating a position gap of a predetermined point in a device area of a wafer based on a stress...
2018/0233388 METHOD AND SYSTEM FOR DETECTING A COOLANT LEAK IN A DRY PROCESS CHAMBER WAFER CHUCK
Device and method of configuring a device to process a wafer is disclosed. The device includes a wafer chuck configured to mount the wafer, a dry wafer...
2018/0233387 Wafer Transport Assembly With Integrated Buffers
A wafer transport assembly includes a first wafer transport module and a second wafer transport module. A buffer module, arranged between the first wafer...
2018/0233386 Platen For Reducing Particle Contamination On A Substrate and a Method Thereof
Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a...
2018/0233385 SUPPORT BODY SEPARATING DEVICE AND SUPPORT BODY SEPARATING METHOD
A supporting member separation apparatus including a light emitting section configured to emit light through a support plate to at least a partial region of a...
2018/0233384 SUBSTRATE LIQUID PROCESSING APPARATUS
A substrate liquid processing apparatus includes a processing tub 34 which is configured to store therein a processing liquid and in which a processing of a...
2018/0233383 SUBSTRATE TREATMENT APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
According to an embodiment, a substrate treatment apparatus includes a tank and a control mechanism. The tank houses a substrate including a silicon oxide film...
2018/0233382 CHIP PACKAGE WITH FAN-OUT STRUCTURE
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the...
2018/0233381 LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE
An electronic package includes a carrier and a semiconductor chip. In a first aspect, a lid is attached to the chip and subsequently the gap between the lid...
2018/0233380 Stack Frame for Electrical Connections and the Method to Fabricate Thereof
A package structure comprises: a plurality of metal parts, wherein each metal part is made of metal and each two adjacent metal parts are spaced apart by a gap...
2018/0233379 METHOD OF FORMING VIA HOLE, ARRAY SUBSTRATE AND METHOD OF FORMING THE SAME AND DISPLAY DEVICE
The present disclosure provides a method of forming a via hole, an array substrate and a method of forming the same and a display device. The method of forming...
2018/0233378 WET ETCHING OF SAMARIUM SELENIUM FOR PIEZOELECTRIC PROCESSING
A subtractive forming method that includes providing a material stack including a samarium and selenium containing layer and an aluminum containing layer in...
2018/0233377 GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT
Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement...
2018/0233376 DRY ETCHING METHOD
A dry etching method includes performing at least two etching steps, and further includes injecting protective gas into an etch chamber for processing between...
2018/0233375 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed...
2018/0233374 ELECTRON-BEAM IRRADIATED AREA ADJUSTMENT METHOD AND ADJUSTMENT SYSTEM, ELECTRON-BEAM IRRADIATED REGION...
Provided is a method of adjusting an electron-beam irradiated area in an electron beam irradiation apparatus that deflects an electron beam with a deflector to...
2018/0233373 SPLITTING METHOD AND USE OF A MATERIAL IN A SPLITTING METHOD
The overall yield of a splitting method for division of a solid-state starting material into at least two solid-state pieces is increased by use of a polymer...
2018/0233372 METHODS FOR FORMING A METALLIC FILM ON A SUBSTRATE BY CYCLICAL DEPOSITION AND RELATED SEMICONDUCTOR DEVICE...
Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a...
2018/0233371 Non-Volatile Flash Memory Cell
A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections;...
2018/0233370 FORMATION OF PURE SILICON OXIDE INTERFACIAL LAYER ON SILICON-GERMANIUM CHANNEL FIELD EFFECT TRANSISTOR DEVICE
Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial...
2018/0233369 FORMATION OF PURE SILICON OXIDE INTERFACIAL LAYER ON SILICON-GERMANIUM CHANNEL FIELD EFFECT TRANSISTOR DEVICE
Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial...
2018/0233368 Method for Integrated Circuit Patterning
An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without...
2018/0233367 WAFER COOLING METHOD
An ion implantation system has a first chamber and a process chamber with a heated chuck. A controller transfers the workpiece between the heated chuck and...
2018/0233366 FORMATION OF RELIEFS ON THE SURFACE OF A SUBSTRATE
A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of...
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