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Patent # Description
2018/0240935 METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE
A method for manufacturing a light emitting device includes: providing a light emitting element having a pad on a top surface thereof; forming an initial ball...
2018/0240934 LIGHT-EMITTING ELEMENT AND METHOD FOR PRODUCING THE SAME
A light-emitting element includes: a sapphire substrate including: a principal surface that is in a c-plane of the sapphire substrate, and a plurality of...
2018/0240933 METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT
A method of manufacturing a light emitting element includes: providing a wafer that comprises: a substrate having a first main surface and a second main...
2018/0240932 TRANSFER PRINTING TEMPLATE AND TRANSFER PRINTING DEVICE OF MICRO LIGHT-EMITTING DIODE
This disclosure provides a transfer printing template, including a transfer substrate, one surface of the substrate has a array of bulges, the bulge surface...
2018/0240931 MICRO-DEVICE PANEL AND MANUFACTURING PROCESS THEREOF
A manufacturing process for a micro-device panel including the following steps is provided. A plurality of micro-device sets are formed on a transferring...
2018/0240930 METHOD AND APPARATUS FOR MANUFACTURING LEAD WIRE FOR SOLAR CELL
A method of manufacturing a lead wire for a solar cell includes heating a wire material by a direct resistance heating or by an induction heating to reduce a...
2018/0240929 RADIATION SENSOR, METHOD OF FORMING THE SENSOR AND DEVICE INCLUDING THE SENSOR
A semiconductor device includes a semiconductor structure formed on a substrate, a gate dielectric formed on a first side of the semiconductor structure, and a...
2018/0240928 OPTOELECTRONIC DEVICES INCLUDING HETEROJUNCTION AND INTERMEDIATE LAYER
Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium...
2018/0240927 TRENCH PROCESS AND STRUCTURE FOR BACKSIDE CONTACT SOLAR CELLS WITH POLYSILICON DOPED REGIONS
A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the...
2018/0240926 Solar Panel with Optical Light Enhancement Device
A double layered superimposed and parallel solar panels having an optical system comprising cylindrical rods and convex lenses at either end of said rods. Said...
2018/0240925 COMPOSITE SYSTEM FOR THE BACK CONTACTING OF PHOTOVOLTAIC MODULES
A composite system for the back contacting of photovoltaic modules includes a metal foil, which has a conducting-path structure, and at least one electrically...
2018/0240924 POLYETHYLENE COMPOSITION FOR A LAYER ELEMENT OF A PHOTVOLTAIC MODULE
The invention relates to a backsheet element for a photovoltaic module comprising at least one layer, which comprises a crosslinked polymer composition, which...
2018/0240923 3D PRINTED THREE-DIMENSIONAL PHOTOVOLTAIC MODULE
A 3D printed three-dimensional photovoltaic system that allows for the absorption of solar energy from various angles. The solar structure has a plurality of...
2018/0240922 FOUR JUNCTION SOLAR CELL AND SOLAR CELL ASSEMBLIES FOR SPACE APPLICATIONS
A four junction solar cell having an upper first solar subcell composed of a semiconductor material having a first band gap; a second solar subcell adjacent to...
2018/0240921 PHOTOELECTRIC CONVERTER
A photoelectric converter includes two semiconductor layers (7A, 7B) forming a p/n junction as a photoelectric conversion layer (1). At least one semiconductor...
2018/0240920 SOLAR CELL, METHOD FOR MANUFACTURING THE SAME, AND ELECTRICAL EQUIPMENT
The present disclosure provides a solar cell, a method for manufacturing the same, and an electrical equipment. The solar cell comprises a first substrate and...
2018/0240919 Solar Cells That Include Quantum Dots
Solar cells that include quantum dots are provided. In particular, a solar panel is provided, the solar panel comprising: a first solar cell comprising: a...
2018/0240917 METHOD OF MANUFACTURING OXIDATION LAYER FOR SOLAR CELL
A method of manufacturing an oxidation layer for a solar cell is disclosed. The method includes exposing a substrate to a wet oxidation atmosphere and forming...
2018/0240916 SEMICONDUCTOR DEVICE
A semiconductor device includes an anode electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second...
2018/0240915 ADVANCED TECHNIQUES TO MANIPULATE THE C-V CHARACTERISTICS OF VARIABLE CAPACITORS
Certain aspects of the present disclosure generally relate to techniques for adjusting or setting a capacitance-versus-voltage (C-V) characteristic of a...
2018/0240914 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
In a method of manufacturing a semiconductor device, a Schottky electrode is formed on an upper surface of a semiconductor substrate. A second region of the...
2018/0240913 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor device including a substrate having a first conductivity type, a first well having a second conductivity type, a first doped region...
2018/0240912 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF
A thin film transistor (TFT) and a method of manufacturing the TFT are disclosed. The TFT (200) includes: a gate (21) formed on a substrate (20); an insulating...
2018/0240911 Thin Film Transistor, Array Substrate and Manufacturing Processes of Them
A thin film transistor and a manufacturing method thereof, and an array substrate are disclosed. The thin film transistor includes a gate electrode, an...
2018/0240910 TRANSISTOR, DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING TRANSISTOR
A transistor includes a buffer layer, an active pattern, and a first insulating layer. The buffer layer is doped with an impurity. The active pattern is on the...
2018/0240909 Method and Structure for FinFET Devices
A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and...
2018/0240908 SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF
A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that...
2018/0240907 FABRICATION OF A VERTICAL FIELD EFFECT TRANSISTOR DEVICE WITH A MODIFIED VERTICAL FIN GEOMETRY
A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate,...
2018/0240906 SWITCHING ELEMENT AND METHOD OF MANUFACTURING THE SAME
A switching element may include a semiconductor substrate, first and second trenches, a gate insulating layer, an interlayer insulating layer covering the...
2018/0240905 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a...
2018/0240904 INTEGRATED CIRCUIT CONNECTION ARRANGEMENT FOR MINIMIZING CROSSTALK
A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the...
2018/0240903 NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
A structure for increasing the concentration of two-dimensional electron gas without lowering mobility is provided. That is, a nitride semiconductor substrate...
2018/0240902 RF DEVICE INTEGRATED ON AN ENGINEERED SUBSTRATE
A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer...
2018/0240901 NITRIDE SEMICONDUCTOR EPITAXIAL STACK STRUCTURE AND POWER DEVICE THEREOF
A nitride semiconductor epitaxial stack structure including: a Silicon substrate; an aluminum-including nucleation layer disposed on the silicon substrate; a...
2018/0240900 GUARD RINGS FOR CASCODE GALLIUM NITRIDE DEVICES
Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least...
2018/0240899 HETEROJUNCTION BIPOLAR TRANSISTOR
A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector...
2018/0240898 HETEROJUNCTION BIPOLAR TRANSISTOR UNIT CELL AND POWER STAGE FOR A POWER AMPLIFIER
A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a...
2018/0240897 HETEROJUNCTION BIPOLAR TRANSISTOR WITH A THICKENED EXTRINSIC BASE
Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is...
2018/0240896 MAGNETO-ELECTRIC LOGIC DEVICES USING SEMICONDUCTOR CHANNEL WITH LARGE SPIN-ORBIT COUPLING
Antiferromagnetic magneto-electric spin-orbit read (AFSOR) logic devices are presented. The devices include a voltage-controlled magnetoelectric (ME) layer...
2018/0240895 SEMICONDUCTOR DEVICE
A semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect...
2018/0240894 PATTERNED SIDEWALL SMOOTHING USING A PRE-SMOOTHED INVERTED TONE PATTERN
Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a...
2018/0240893 FORMING NON-LINE-OF-SIGHT SOURCE DRAIN EXTENSION IN AN NMOS FINFET USING N-DOPED SELECTIVE EPITAXIAL GROWTH
A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the...
2018/0240892 PATTERNED SIDEWALL SMOOTHING USING A PRE-SMOOTHED INVERTED TONE PATTERN
Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a...
2018/0240891 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and...
2018/0240890 METAL OXIDE SEMICONDUCTOR (MOS) ISOLATION SCHEMES WITH CONTINUOUS ACTIVE AREAS SEPARATED BY DUMMY GATES AND...
Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy...
2018/0240889 SEMICONDUCTOR DEVICES HAVING EQUAL THICKNESS GATE SPACERS
A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET...
2018/0240888 METHOD FOR MANUFACTURING A TRANSISTOR AND METHOD FOR MANUFACTURING A RING OSCILLATOR USING THE SAME
In a method for manufacturing a transistor, a gate structure may be formed on a semiconductor substrate. A first material layer may be formed on the gate...
2018/0240887 Semiconductor Device and Method of Manufacturing the Same
A method for use in manufacturing an electronic component comprises forming a layered structure comprising a dielectric structure layer, a channel layer and a...
2018/0240886 GRAPHENE HETEROLAYERS FOR ELECTRONIC APPLICATIONS
A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating...
2018/0240885 SIMPLIFIED GATE TO SOURCE/DRAIN REGION CONNECTIONS
Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate...
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