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Patent # Description
2018/0240833 BACKSIDE ILLUMINATED IMAGE SENSOR WITH IMPROVED CONTACT AREA
An image sensor includes a semiconductor material having a front side and a back side opposite the front side. The image sensor also includes a shallow trench...
2018/0240832 SOLID STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD, SEMICONDUCTOR WAFER, AND ELECTRONIC APPARATUS
The present technology relates to a solid state image pickup device and a production method, a semiconductor wafer, and an electronic apparatus by which the...
2018/0240831 SOLID-STATE IMAGING APPARATUS
A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member...
2018/0240830 Surface Treatment for BSI Image Sensors
A method comprises forming an image sensor adjacent to a first side of a substrate, thinning a second side of the substrate, performing a halogen treatment on...
2018/0240829 SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC DEVICE
The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic device capable of further improving quality. A...
2018/0240828 MOLDED IMAGE SENSOR CHIP SCALE PACKAGES AND RELATED METHODS
Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second...
2018/0240827 PACKAGE STRUCTURE AND PACKAGING METHOD
A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a...
2018/0240826 IMAGE SENSOR
An image sensor device includes a photoelectric conversion element configured to receive incident light and generate photocharges in response to the received...
2018/0240825 SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE
The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided...
2018/0240824 OPTOELECTRONIC MODULE WITH CUSTOMIZABLE SPACERS
The disclosure describes customizable optoelectronic modules and methods for standardizing a plurality of the customizable optoelectronic modules. The...
2018/0240823 SOLID-STATE IMAGING ELEMENT AND ELECTRONIC APPARATUS
The present disclosure relates to a solid-state imaging element and an electronic apparatus, in which the number of wires controlling readout can be reduced in...
2018/0240822 DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
A display apparatus includes a substrate, a patterned layer, a light-shielding layer, a first electrode, a second electrode, an electroluminescent layer (EL),...
2018/0240821 INTEGRATION OF SILICON THIN-FILM TRANSISTORS AND METAL-OXIDE THIN FILM TRANSISTORS
This disclosure relates generally to the three-dimensional (3D) integrated thin-film transistors (TFTs) with silicon and metal-oxide (MO) semiconductors as the...
2018/0240820 ELECTRO-OPTICAL AND OPTOELECTRONIC DEVICES
The present invention is notably directed to an electro-optical device. The latter comprises a layer structure with: a silicon substrate; a buried oxide layer...
2018/0240819 Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same
A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is...
2018/0240818 METHOD FOR MANUFACTURING TFT SUBSTRATE AND STRUCTURE THEREOF
The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate arranges a...
2018/0240817 Liquid Crystal Display Device and Electronic Device
To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply...
2018/0240816 ARRAY SUBSTRATE AND DISPLAY DEVICE
An array substrate and a display device are provided. The array substrate includes: a base substrate; and first leads, third leads, and second leads connecting...
2018/0240815 FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold...
2018/0240814 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are...
2018/0240813 SEMICONDUCTOR DEVICE
A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source...
2018/0240812 3D MEMORY DEVICE
A 3D memory device, comprising a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an array of strings of memory...
2018/0240811 VERTICAL SEMICONDUCTOR MEMORY DEVICE STRUCTURES INCLUDING VERTICAL CHANNEL STRUCTURES AND VERTICAL DUMMY STRUCTURES
A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a...
2018/0240810 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
According to an embodiment, a semiconductor memory device includes a pillar member, a plurality of insulating layers arranged on an outer peripheral surface of...
2018/0240809 Method of Manufacturing a Semiconductor Device
A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate;...
2018/0240808 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate...
2018/0240807 NON-VOLATILE MEMORY DEVICE
According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive...
2018/0240806 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped...
2018/0240805 METHOD OF MANUFACTURING VERTICAL MEMORY DEVICES
A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the...
2018/0240804 FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region. The ferroelectric memory device includes a...
2018/0240803 FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure disposed on the...
2018/0240802 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the...
2018/0240801 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential...
2018/0240800 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor...
2018/0240799 HIGH-K GATE DIELECTRIC AND METAL GATE CONDUCTOR STACK FOR FIN-TYPE FIELD EFFECT TRANSISTORS FORMED ON TYPE...
An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least...
2018/0240798 SEMICONDUCTOR DEVICE WITH DUMMY PATTERN IN HIGH-VOLTAGE REGION AND METHOD OF FORMING THE SAME
A semiconductor device includes a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern...
2018/0240797 STACKED BODY
A stacked body according to an embodiment of the present technology includes: a plurality of transistors; a first substrate; and a second substrate that is...
2018/0240796 SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME
A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in...
2018/0240795 SEMICONDUCTOR DEVICE
A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode provided above the semiconductor substrate; a sense anode...
2018/0240794 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes...
2018/0240793 LED CHIP HAVING ESD PROTECTION
Disclosed herein is a light emitting diode chip having ESD protection. An exemplary embodiment provides a flip-chip type light emitting diode chip, which...
2018/0240792 SEMICONDUCTOR DEVICE
A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode...
2018/0240791 METHOD OF FORMING A SEMICONDUCTOR DEVICE AND METHOD THEREFOR
In one embodiment, a method of forming a HEM diode may comprise forming the HEM diode with high forward voltage that is greater than one of a gate-to-source...
2018/0240790 Method and Structure for Semiconductor Mid-End-Of-Line (MEOL) Process
A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and...
2018/0240789 STACKABLE ELECTRONIC PACKAGE AND METHOD OF FABRICATING SAME
An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first...
2018/0240788 INORGANIC INTERPOSER FOR MULTI-CHIP PACKAGING
Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low...
2018/0240787 HALF-BRIDGE POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME
A half-bridge power semiconductor module has an insulating wiring substrate including a single insulating plate, and a positive electrode wiring conductor, a...
2018/0240786 SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES
A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the...
2018/0240785 STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUPPORT MEMBERS AND ASSOCIATED SYSTEMS AND METHODS
Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
2018/0240784 SEMICONDUCTOR DEVICE
A semiconductor device includes multiple semiconductor chips and a control unit. Each of the semiconductor chips has multiple signal processing units that can...
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