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Patent # Description
2018/0248050 METHOD OF MANUFACTURING A FINFET VARACTOR
A method of manufacturing a varactor transistor includes providing a semiconductor structure including a semiconductor fin and an initial insulator layer on...
2018/0248049 SCHOTTKY DIODE AND METHOD OF MANUFACTURING THE SAME
A Schottky diode comprises: a substrate; a first semiconductor layer located on the substrate; a second semiconductor layer located on the first semiconductor...
2018/0248048 WATER-INSENSITIVE GAS SENSOR USING POLYMER-ENCAPSULATED Pt-AlGaN/GaN DIODES
A hydrogen sensor can include a substrate, an Ohmic metal disposed on the substrate, a nitride layer disposed on the substrate and having a first window...
2018/0248047 SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SAME AND ALIPHATIC POLYCARBONATE
It is an object of the invention to provide a thin film transistor and a method for producing the same, which will easily achieve self-aligned formation of a...
2018/0248046 METHODS OF FORMING UPPER SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE
A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower...
2018/0248045 SEMICONDUCTOR DEVICE
A semiconductor device may include a base substrate, a first thin-film transistor ("TFT") provided on the base substrate, a second TFT provided on the base...
2018/0248044 FLEXIBLE SUBSTRATE STRUCTURE, FLEXIBLE TRANSISTOR AND METHOD FOR FABRICATING THE SAME
A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided....
2018/0248043 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating...
2018/0248042 INDEPENDENT GATE FINFET WITH BACKSIDE GATE CONTACT
A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the...
2018/0248041 INDEPENDENT GATE FINFET WITH BACKSIDE GATE CONTACT
A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the...
2018/0248040 CHARGE CARRIER TRANSPORT FACILITATED BY STRAIN
A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second...
2018/0248039 HIGH-VOLTAGE TRANSISTOR WITH SELF-ALIGNED ISOLATION
A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is...
2018/0248038 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first...
2018/0248037 VERTICAL FET STRUCTURE
Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more...
2018/0248036 ASYMMETRIC VERTICAL DEVICE
A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate...
2018/0248035 VERTICAL SEMICONDUCTOR DEVICE
A vertical transistor structure includes a first transistor and a second transistor. The first transistor includes a first lower electrode connected to a...
2018/0248034 ASYMMETRIC VERTICAL DEVICE
A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate...
2018/0248033 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body...
2018/0248032 TFT BACKPLANE AND MANUFACTURING METHOD THEREOF
A TFT backplane structure includes a gate insulating layer that includes a three-layered portion, which includes, from bottom up, a dielectric layer, a SiNx...
2018/0248031 METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE
There is provided a manufacturing method for a thin-film transistor substrate, which enables to excellently perform alignment between an annealed region of a...
2018/0248030 SELF-ALIGNED GATE CUT WITH POLYSILICON LINER OXIDATION
A method of forming a semiconductor device that includes forming a gate structure over a plurality of fin structures, wherein the gate structure provides a...
2018/0248029 SELF-ALIGNED GATE CUT WITH POLYSILICON LINER OXIDATION
A method of forming a semiconductor device that includes forming a gate structure over a plurality of fin structures, wherein the gate structure provides a...
2018/0248028 HIGH-ELECTRON-MOBILITY TRANSISTORS WITH HETEROJUNCTION DOPANT DIFFUSION BARRIER
III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A...
2018/0248027 SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate; a channel layer constituted of a single nitride semiconductor on the substrate; a first barrier layer which is a...
2018/0248026 SEMICONDUCTOR DEVICE
A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is...
2018/0248025 FINFET SCR WITH SCR IMPLANT UNDER ANODE AND CATHODE JUNCTIONS
SCRs are a must for ESD protection in low voltage--high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print...
2018/0248024 POWER SEMICONDUCTOR DEVICE
A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body having a front side, a backside, a first load terminal,...
2018/0248023 BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME
A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are...
2018/0248022 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device comprise a substrate, source/drain regions, a channel region, a gate dielectric layer and a gate conductive layer, wherein the gate...
2018/0248021 FORMATION OF INNER SPACER ON NANOSHEET MOSFET
A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon...
2018/0248020 Method For Non-Resist Nanolithography
A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening...
2018/0248019 A METHOD FOR FORMING APPARATUS COMPRISING TWO DIMENSIONAL MATERIAL
A method and apparatus, the method comprising: forming at least two electrodes (23) on a release layer wherein the at least two electrodes are configured to...
2018/0248018 Semiconductor Devices Having Vertical Transistors with Aligned Gate Electrodes
A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater...
2018/0248017 COMPOSITE SPACER ENABLING UNIFORM DOPING IN RECESSED FIN DEVICES
A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial...
2018/0248016 SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment includes a semiconductor region, a gate electrode, and a first gate insulating film provided between the...
2018/0248015 PASSIVATION OF TRANSISTOR CHANNEL REGION INTERFACES
Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated...
2018/0248014 INVERTED MOSFET WITH SCALING ADVANTAGE
After forming a gate structure wrapping around a suspended channel portion of a semiconductor fin located on an insulator layer, a gate cap is formed atop the...
2018/0248013 HIGH VOLTAGE FIELD EFFECT TRANSISTOR WITH LATERALLY EXTENDED GATE DIELECTRIC AND METHOD OF MAKING THEREOF
A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes...
2018/0248012 METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED THEREBY
Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a...
2018/0248011 SEMICONDUCTOR DEVICE CONTACTS WITH INCREASED CONTACT AREA
Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing...
2018/0248010 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are...
2018/0248008 SEMICONDUCTOR DEVICE
A semiconductor device in which an interlayer insulation film covers striped gate electrodes with a thickness larger than a thickness of a gate oxide film. The...
2018/0248007 ENCAPSULATED NANOSTRUCTURES AND METHOD FOR FABRICATING
Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods...
2018/0248006 BODY CONTACT LAYOUTS FOR SEMICONDUCTOR STRUCTURES
Body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a semiconductor structure comprises: a plurality of...
2018/0248005 METHODS FOR DOPING A SUB-FIN REGION OF A SEMICONDUCTOR STRUCTURE BY BACKSIDE REVEAL AND ASSOCIATED DEVICES
Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins...
2018/0248004 DEUTERIUM-BASED PASSIVATION OF NON-PLANAR TRANSISTOR INTERFACES
Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated...
2018/0248003 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between...
2018/0248002 SILICON CARBIDE SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE
In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n.sup.++-type semiconductor substrate. Next, a trench is...
2018/0248001 SEGMENTED GUARD-RING AND CHIP EDGE SEALS
The present disclosure relates to semiconductor structures and, more particularly, to segmented guard-ring and chip edge seals and methods of manufacture. The...
2018/0248000 Vertical Transistor Device with a Variable Gate Dielectric Thickness
A vertical transistor device includes a silicon-carbide substrate, a gate trench formed in the silicon-carbide substrate, a body region adjacent the gate...
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