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Patent # Description
2018/0247949 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including...
2018/0247948 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system classifies nonvolatile memory dies connected to channels into die groups such that each of the nonvolatile memory...
2018/0247947 MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die...
2018/0247946 NEUROMORPHIC DEVICE
A neuromorphic device may include: a plurality of row lines extending in a first direction; a plurality of additional row lines extending in the first...
2018/0247945 METAL FINFET ANTI-FUSE
Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance...
2018/0247944 NOR FLASH MEMORY AND MANUFACTURING METHOD THEREOF
An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of...
2018/0247943 SEMICONDUCTOR STRUCTURE WITH CAPACITOR LANDING PAD AND METHOD OF MAKING THE SAME
A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad...
2018/0247942 Memory Arrays
Some embodiments include a memory array having rows of fins. Each fin has at least one channel region. Each channel region extends from a first source/drain...
2018/0247941 CAPACITOR FOR SEMICONDUCTOR MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME
A capacitor for a semiconductor memory element includes a lower electrode, a dielectric layer disposed on the lower electrode and including titanium oxide, and...
2018/0247940 THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICES
A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure...
2018/0247939 TECHNIQUES FOR CONTROLLING TRANSISTOR SUB-FIN LEAKAGE
Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar...
2018/0247938 FABRICATION OF FIN FIELD EFFECT TRANSISTORS UTILIZING DIFFERENT FIN CHANNEL MATERIALS WHILE MAINTAINING...
A method of forming vertical fins on a substrate at the same time, the method including, forming a mask segment on a first region of the substrate while...
2018/0247937 Method of Forming a Single Metal that Performs N Work Function and P Work Function in a High-K/Metal Gate Process
A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a...
2018/0247936 FIELD EFFECT TRANSISTORS WITH REDUCED PARASITIC RESISTANCES AND METHOD
Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during...
2018/0247935 Methods for Forming STI Regions in Integrated Circuits
A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a...
2018/0247934 DIODE HAVING A PLATE-SHAPED SEMICONDUCTOR ELEMENT
A diode is provided having a plate-shaped semiconductor element that includes a first side and a second side, the first side being connected by a first...
2018/0247933 COMPOUND SEMICONDUCTOR TRANSISTOR AND HIGH-Q PASSIVE DEVICE SINGLE CHIP INTEGRATION
An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound...
2018/0247932 VOLTAGE BALANCED STACKED CLAMP
Embodiments of the present invention provide computer system for balancing voltages during voltage division. More specifically, circuit performance is enhanced...
2018/0247931 VOLTAGE BALANCED STACKED CLAMP
Embodiments of the present invention provide a computer program product for balancing voltages during voltage division. More specifically, circuit performance...
2018/0247930 VOLTAGE BALANCED STACKED CLAMP
Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is...
2018/0247929 SEMICONDUCTOR DEVICES AND METHODS TO ENHANCE ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS, LATCH-UP, AND HOT...
The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure...
2018/0247928 ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE AND METHOD FOR OPERATING AN ESD PROTECTION DEVICE
Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD...
2018/0247927 DEVICE AND METHOD FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD...
2018/0247926 SEMICONDUCTOR DEVICE
An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of...
2018/0247925 ESD PROTECTION CIRCUIT WITH INTEGRAL DEEP TRENCH TRIGGER DIODES
Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a...
2018/0247924 ELECTRONICS PACKAGE HAVING A MULTI-THICKNESS CONDUCTOR LAYER AND METHOD OF MANUFACTURING THEREOF
An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first...
2018/0247923 SEMICONDUCTOR MODULE
A semiconductor module, comprises a substrate plate; a semiconductor switch chip and a diode chip attached to a collector conductor on the substrate plate,...
2018/0247922 Illuminated Faceplate And Method For Producing Such An Illuminated Faceplate
A luminous panel includes a substrate having electric connections and an array of microchips secured to the substrate and connected to the electric connections...
2018/0247921 Packaging a Substrate with an LED into an Interconnect Structure Only Through Top Side Landing Pads on the...
Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass...
2018/0247920 DISPLAY DEVICE AND IMAGING DEVICE
A display device (1) includes a substrate (11) having a first surface (S1) and a second surface (S2) that face each other, and having a plurality of light...
2018/0247919 METHOD FOR MANUFACTURING THREE DIMENSIONAL INTEGRATED CIRCUIT PACKAGE
A method for manufacturing a three dimensional integrated circuit (3DIC) package includes stacking a plurality of semiconductor chips vertically and...
2018/0247918 STACKED TRANSISTOR PACKAGES
Transistor packages in space-constrained applications are disclosed. An apparatus may comprise a first transistor package and a second transistor package,...
2018/0247917 ELECTRONIC CIRCUIT DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC CIRCUIT DEVICE
An electronic circuit device includes a first electronic component having a set of first terminals disposed at a first pitch on a first surface, and a second...
2018/0247916 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various...
2018/0247915 SEMICONDUCTOR DEVICE ASSEMBLIES WITH ELECTRICALLY FUNCTIONAL HEAT TRANSFER STRUCTURES
Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one...
2018/0247913 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a...
2018/0247912 THERMALLY CONDUCTIVE MOLDING COMPOUND STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES
A method of forming a semiconductor package includes attaching a thermal conductivity layer to a chip. The chip has a first surface and a second surface. The...
2018/0247911 Semiconductor Device
A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor...
2018/0247910 ACRYLIC RESIN COMPOSITION FOR SEALING, CURED PRODUCT OF SAME, METHOD FOR PRODUCING SAME, SEMICONDUCTOR DEVICE...
A sealing acrylic resin composition contains a thermosetting acrylic resin in liquid phase, an organic peroxide, and an inorganic filler in a content...
2018/0247909 Method and System for Packing Optimization of Semiconductor Devices
Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging...
2018/0247908 GRID ARRAY CONNECTION DEVICE AND METHOD
A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such...
2018/0247907 Semiconductor Device And Bump Formation Process
A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the...
2018/0247906 METHODS OF FORMING SEMICONDUCTOR STRUCTURES HAVING A PATTERNED SURFACE STRUCTURE
A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation...
2018/0247905 Integrated Devices in Semiconductor Packages and Methods of Forming Same
An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric...
2018/0247904 SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PROCESS
The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a...
2018/0247903 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
Provided are a semiconductor device in which a fuse element can be stably fused without generating a crack in a base insulating film even when a protective...
2018/0247902 TIMING BASED CAMOUFLAGE CIRCUIT
In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is...
2018/0247901 INTEGRATED CIRCUIT WITH DETECTION OF THINNING VIA THE BACK FACE AND DECOUPLING CAPACITORS
A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A...
2018/0247900 SEMICONDUCTOR PACKAGE
Some embodiments relate to a semiconductor package. The semiconductor package includes a redistribution layer (RDL) including a first metal layer and a second...
2018/0247899 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor device includes an insulating film. The insulating film includes a first insulating particle, and a second...
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