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Patent # Description
2018/0247898 WIRING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC MODULE
A wiring board includes an insulating substrate, mount electrodes arranged to face each other on a first main surface of the insulating substrate along a pair...
2018/0247897 SEMICONDUCTOR PACKAGE HAVING AN ELECTRO-MAGNETIC INTERFERENCE SHIELDING OR ELECTRO-MAGNETIC WAVE SCATTERING...
Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that...
2018/0247896 METHOD OF ARRANGING A PLURALITY OF SEMICONDUCTOR STRUCTURAL ELEMENTS ON A CARRIER AND CARRIER COMPRISING A...
A method of arranging a plurality of semiconductor structural elements on a carrier includes arranging at least some of the semiconductor structural elements...
2018/0247895 SEMICONDUCTOR DEVICE
A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and...
2018/0247894 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an...
2018/0247893 SEMICONDUCTOR DEVICE
A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer...
2018/0247892 SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, AND LOAD DRIVING DEVICE
On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input...
2018/0247891 METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on...
2018/0247890 Semiconductor Structure and Manufacturing Method Thereof
A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive...
2018/0247889 SEMICONDUCTOR DEVICE
This semiconductor device has a plurality of external terminals arranged in an array on a bottom surface of a package. The plurality of external terminals...
2018/0247888 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device includes a semiconductor chip, an electrode electrically connected to the semiconductor chip, the electrode including a looped portion,...
2018/0247887 PRINTED CIRCUIT BOARD, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A printed circuit board (PCB) is provided as follows. A first connection pad and a second connection pad are disposed on a first surface and a second surface...
2018/0247886 ELECTRONIC PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
The disclosure provides a method for manufacturing an electronic package structure, including disposing on a carrier an electronic component and a conductive...
2018/0247885 ELECTRONIC ASSEMBLY WITH ENHANCED THERMAL DISSIPATION
In accordance with one aspect of the disclosure, an electronic assembly comprises a semiconductor device with a first side and a second side opposite the first...
2018/0247884 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by...
2018/0247883 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is...
2018/0247882 CHIP-ON-FILM SEMICONDUCTOR PACKAGES AND DISPLAY APPARATUS INCLUDING THE SAME
Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF...
2018/0247881 Electronic Apparatus
A leaf spring is disposed between a circuit board and a upper shield. The leaf spring biases a heat sink toward the circuit board through a connecting member....
2018/0247880 Chip Packaging System
This application provides a chip packaging system, including multiple chips, a substrate, a heat dissipating component, and at least one thermoelectric...
2018/0247879 High Power Gallium Nitride Devices and Structures
Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in...
2018/0247878 CIRCUIT SUBSTRATE, AND ELECTRONIC DEVICE INCLUDING SAME
A circuit substrate is provided with a base formed of ceramics. It includes a first face a second face; and a through hole penetrating from the first face to...
2018/0247877 DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME
A display panel includes first and second test lines connected to the each of data lines, extending in the second direction, and arranged in the first...
2018/0247876 STACKED SEMICONDUCTOR DEVICE
A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die, and suitable for communicating with allocated...
2018/0247875 METHODS FOR DEPOSITING FILMS ON SENSITIVE SUBSTRATES
Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments,...
2018/0247874 INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION
An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face...
2018/0247873 GERMANIUM DUAL-FIN FIELD EFFECT TRANSISTOR
In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain...
2018/0247872 METHOD OF SEPARATING SEMICONDUCTOR DIES FROM A SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE ASSEMBLY AND...
Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions...
2018/0247871 METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT
A method of manufacturing a semiconductor element includes: providing a wafer having a semiconductor layered body on a sapphire substrate; irradiating a laser...
2018/0247870 METHOD OF PROCESSING WAFER AND PROTECTIVE SHEETING FOR USE IN THIS METHOD
A wafer has on one side a device area with a plurality of devices, partitioned by a plurality of division lines, and a peripheral marginal area formed around...
2018/0247869 Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral Trenches
A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the...
2018/0247868 ELECTRONIC COMPONENT MANUFACTURING METHOD
An electronic component manufacturing method includes preparing a structure including a conductive member, forming a seed metal layer including first and...
2018/0247867 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure includes a semiconductor substrate having fins and gate structures on the fins. A protective layer is formed on top surfaces of the...
2018/0247866 MODULATING THE MICROSTRUCTURE OF METALLIC INTERCONNECT STRUCTURES
Tooling apparatus and methods are provided to fabricate semiconductor devices in which controlled thermal annealing techniques are utilized to modulate...
2018/0247865 HIGH PERFORMANCE MIDDLE OF LINE INTERCONNECTS
A method for formation of multi-level contact structures with reduced contact resistance is provided. The contact resistance of the multi-level contact...
2018/0247864 SELF-ALIGNED PATTERN FORMATION FOR A SEMICONDUCTOR DEVICE
A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of...
2018/0247863 METHOD OF PATTERNING TARGET LAYER
The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure....
2018/0247862 Method for Defining Patterns for Conductive Paths in Dielectric Layer
The present disclosure provides a method for defining patterns for conductive paths in a dielectric layer. An example method includes forming a mask layer and...
2018/0247861 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
In a manufacturing method for a semiconductor device formed over an SOI substrate, a first epitaxial layer is partially formed over an outer circumference end...
2018/0247860 METHOD FOR PRODUCING BONDED SOI WAFER
A method for producing a bonded SOI wafer by bonding a bond wafer and a base wafer, each being formed of a silicon single crystal, together with a silicon...
2018/0247859 METHOD AND APPARATUS FOR SEMICONDUCTOR DEVICE WITH REDUCED DEVICE FOOTPRINT
A semiconductor device is provided. The semiconductor device includes a semiconductor layer, and a trench formed in a top surface of the semiconductor layer....
2018/0247858 FILM DEPOSITION METHOD AND PLASMA PROCESSING APPARATUS
A film deposition method includes maintaining an inside of a chamber to have a predetermined pressure, cooling a stage, on which the object to be processed...
2018/0247857 SEMICONDUCTOR WAFER AND METHOD FOR PROCESSING A SEMICONDUCTOR WAFER
According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one...
2018/0247856 Structure Having Isolated Deep Substrate Vias With Decreased Pitch And Increased Aspect Ratio And Related Method
A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a...
2018/0247855 Stage Apparatus and Charged Particle Beam Apparatus
An object of the invention is to provide a stage apparatus that realizes compatibility between long stroke driving and reduction of a burden on a drive...
2018/0247854 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE HOLDING DEVICE
A plate-like base of a substrate holder has an upper surface perpendicular to a central axis. A supporter is disposed circumferentially around the central part...
2018/0247853 ELECTROSTATIC CHUCK TABLE USING METHOD
An electrostatic chuck table includes a plate-shaped base portion capable of transmitting a laser beam to be applied to a workpiece and an electrostatic...
2018/0247852 SUBSTRATE FIXTURE AND SUBSTRATE FIXING DEVICE
A substrate fixture includes a monopolar chuck main body comprising an insulated plate and an electrode embedded in the insulated plate, a tray placed on the...
2018/0247851 METHOD FOR DETERMINING FRONT AND BACK OF SINGLE-CRYSTAL WAFER
A method for determining front and back of a single-crystal wafer including: using, as the single-crystal wafer, one having a crystal plane which is laterally...
2018/0247850 METHOD AND APPARATUS FOR SUBSTRATE TRANSFER AND RADICAL CONFINEMENT
Embodiments of the present invention provide an apparatus for transferring substrates and confining a processing environment in a chamber. One embodiment of...
2018/0247849 INTERNAL PURGE DIFFUSER WITH OFFSET MANIFOLD
A purge tower assembly for a substrate container. The assembly may include a purge interface body, including a base portion and a top portion, for mounting to...
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