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Patent # Description
2018/0246834 Processor With Reconfigurable Pipelined Core And Algorithmic Compiler
An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a system. The reusable algorithmic pipelined core is a...
2018/0246833 DYNAMIC PARTITION OF PCIe DISK ARRAYS BASED ON SOFTWARE CONFIGURATION / POLICY DISTRIBUTION
This disclosure relates to methods and systems for dynamically partitioning of PCIe disk arrays based on software configuration/policy distribution. In one...
2018/0246832 PERIPHERAL DISCONNECTION SWITCH SYSTEM AND METHOD
A peripheral disconnection switch system and method are provided. The system comprises at least one peripheral connected to a processor, and a hardware switch...
2018/0246831 DEVICE AND SYSTEM FOR AGGREGATING NETWORKS AND SERVING DATA FROM THOSE NETWORKS TO COMPUTERS
Disclosed herein, in one example, is a device for aggregating networks and serving data from those networks to computers for integrating information from...
2018/0246830 INBAND MESSAGING METHOD FOR INTEGRATED TYPE-C UNIVERSAL SERIAL BUS DETECTION USING ENHANCED SERIAL PERIPHERAL...
A method implemented by a system on a chip (SOC) system executing an enhance serial peripheral interconnect (eSPI) master. The method to receive an alert from...
2018/0246829 POWER AWARE ARBITRATION FOR BUS ACCESS
Systems and methods for operating a bus interface unit include queues for receiving and storing one or more words from one or more agents for transmission on...
2018/0246828 SHARED RESOURCE ACCESS ARBITRATION METHOD, AND SHARED RESOURCE ACCESS ARBITRATION DEVICE AND SHARED RESOURCE...
Provided is a shared resource access arbitration method of a shared resource access arbitration apparatus, the shared resource access arbitration method...
2018/0246827 DELIVERING INTERRUPTS TO USER-LEVEL APPLICATIONS
Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of...
2018/0246826 AGGREGATION OF INTERRUPTS USING EVENT QUEUES
Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an...
2018/0246825 PACKET PROCESSING EFFICIENCY BASED INTERRUPT RATE DETERMINATION
Interrupt rate determination can include instructions to determine a quantity of instances of packet processing by an operating system during a first period of...
2018/0246824 SYSTEM PROVIDED WITH COMPUTER AND STORAGE APPARATUS AND METHOD FOR CONTROL OF SYSTEM
A system including a computer provided with a memory configured to store a program and a first CPU (central processing unit) configured to execute the program...
2018/0246823 COMPUTER SYSTEM AND APPARATUS MANAGEMENT METHOD
Provided is a computer system, comprising a plurality of devices and a plurality of management computers. The devices further comprise one or more objects. The...
2018/0246822 APPARATUSES AND METHODS FOR ASYMMETRIC INPUT/OUTPUT INTERFACE FOR A MEMORY
Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The...
2018/0246821 MEMORY SYSTEM AND CONTROL METHOD
A memory package in which a plurality of stacked non-volatile memory dies is connected to one another through a plurality of vertical vias is used in a memory...
2018/0246820 MULTIPLE LINKED LIST DATA STRUCTURE
A system and method for maintaining information of pending operations are described. A buffer uses multiple linked lists implementing a single logical queue...
2018/0246819 ASYNCHRONOUS FINITE STATE MACHINES
A sequential asynchronous system and a method for operating the same. The method includes operating a first asynchronous finite state machine at a first clock...
2018/0246818 PHYSICAL ADDRESS RANDOMIZATION FOR SECURE ENCRYPTED MEMORY
An operating system (OS) receives a request to allocate a physical memory page to an address space of an application. The OS maintains a data structure that...
2018/0246817 INPUT/OUTPUT DIRECT MEMORY ACCESS DURING LIVE MEMORY RELOCATION
A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a...
2018/0246816 STREAMING TRANSLATION LOOKASIDE BUFFER
Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory...
2018/0246815 SHARING TRANSLATION LOOKASIDE BUFFER RESOURCES FOR DIFFERENT TRAFFIC CLASSES
Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels,...
2018/0246814 PER-PAGE CONTROL OF PHYSICAL ADDRESS SPACE DISTRIBUTION AMONG MEMORY MODULES
Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing...
2018/0246813 ACCESSING OBJECTS VIA OBJECT REFERENCES
An example system in accordance with an aspect of the present disclosure includes a cache engine, a validate engine, and an access engine. The cache engine is...
2018/0246812 CACHING MECHANISMS FOR AGGREGATED INFORMATION CALCULATION AND INJECTION FOR APPLICATION CONTAINERS
Embodiments for caching extracted information from application containers by one or more processors. Upon extracting relevant information from a temporary...
2018/0246811 HEURISTIC METHOD TO CONTROL FETCHING OF METADATA FROM A CACHE HIERARCHY
Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in...
2018/0246810 Transparent Host-Side Caching of Virtual Disks Located on Shared Storage
Techniques for using a cache to accelerate virtual machine (VM) I/O are provided. In one embodiment, a host system can intercept an I/O request from a VM...
2018/0246809 COLUMN STORE MAIN FRAGMENTS IN NON-VOLATILE RAM
A system includes a non-volatile random access memory storing a column store main fragment of a column of a database table, and a processing unit to read the...
2018/0246808 INFORMATION PROCESSING APPARATUS
An information processing apparatus includes a receiving unit that receives data from the outside, a first memory space to which data is written from the...
2018/0246807 LIFECYCLE MANAGEMENT FOR DATA IN NON-VOLATILE MEMORY
A system includes creation of a first fragment of a first database column in a volatile memory system, reception of a first pointer to a first block of a...
2018/0246806 MEMORY MANAGEMENT IN MULTI-PROCESSOR ENVIRONMENTS
To manage memory in a multi-processing system, a memory budget is assigned to each of a number of agents within the multi-processing system. A portion of...
2018/0246805 SYSTEM AND METHOD FOR DETERMINING REQUIREMENTS FOR TESTING SOFTWARE
A computer-implemented method, computer program product, and system is provided for determining requirements for testing software. In an implementation, a...
2018/0246804 SYSTEM AND METHOD FOR DETERMINING REQUIREMENTS FOR TESTING SOFTWARE
A computer-implemented method, computer program product, and system is provided for determining requirements for testing software. In an implementation, a...
2018/0246803 TARGETED SOFTWARE TESTING
To reduce the time for testing an application, a software testing system can identify and select test scripts that are targeted toward program code in the...
2018/0246802 BACKWARD COMPATIBILITY TESTING OF SOFTWARE IN A MODE THAT DISRUPTS TIMING
A device may be run in a timing testing mode in which the device is configured to disrupt timing of processing that takes place on the one or more processors...
2018/0246801 CONTROLLING A SYSTEM UNDER TEST USING A COGNITIVE CONTROL BASED TEST RUNNER
Embodiments comprise cognitive control of an application by a processor. Current state data representing a current state of an application may be collected...
2018/0246800 ABNORMAL TIMING BREAKPOINTS
Embodiments of the present invention provide a system, method, and program product for an abnormal timing breakpoints. A computer determines a code section,...
2018/0246799 ABNORMAL TIMING BREAKPOINTS
Embodiments of the present invention provide a system, method, and program product for an abnormal timing breakpoints. A computer determines a code section,...
2018/0246798 Method and a system for monitoring batch processing of applications executed in IT infrastructure
A method and a system for monitoring batch processing of applications executed in IT infrastructure. The method being implemented by monitoring software...
2018/0246797 IDENTIFYING AND MONITORING NORMAL USER AND USER GROUP INTERACTIONS
The invention relates to a network monitoring system for computer systems. According to an aspect of the invention, there is provided a method for monitoring...
2018/0246796 MECHANISM TO PROVIDE BACK-TO-BACK TESTING OF MEMORY CONTROLLER OPERATION
Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test...
2018/0246795 SYSTEM AND METHOD FOR SIMULATION RESULTS ANALYSIS AND FAILURES DEBUG USING A DESCRIPTIVE TRACKING HEADER
The present disclosure relates to system(s) and method(s) for simulation results analysis and failures debug using a Descriptive Tracking Header. The method...
2018/0246794 METHODS FOR MONITORING AND MANAGING MEMORY DEVICES
The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes scanning a first memory...
2018/0246793 DATA STRIPPING, ALLOCATION AND RECONSTRUCTION
A method for data stripping, allocation and reconstruction in an active drive storage system including a plurality of active object storage devices, each of...
2018/0246792 MIRRORING WRITES OF RECORDS TO MAINTAIN ATOMICITY FOR WRITING A DEFINED GROUP OF RECORDS TO MULTIPLE TRACKS
Provided are a computer program product, system, and method for mirroring writes of records to maintain atomicity for writing a defined group of records to...
2018/0246791 HIGH-AVAILABILITY CLUSTER ARCHITECTURE AND PROTOCOL
Methods and systems are provided for an improved cluster-based network architecture. According to one embodiment, an active connection is established between a...
2018/0246790 System and Method for Data Restore Flexibility on Dual Channel NVDIMMs
A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a...
2018/0246789 INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
An information processing apparatus described herein includes a hard disk drive device and a controller. The controller is configured to carry out a...
2018/0246788 METHOD AND APPARATUS FOR RECOVERING IN-MEMORY DATA PROCESSING SYSTEM
Example implementations involve a plurality of servers, network, and storage systems, wherein some of the servers may execute data programs and store primary...
2018/0246787 METHOD FOR DETECTING AN UNCORRECTABLE ERROR IN A NON-VOLATILE MEMORY OF A MICROCONTROLLER
A method for detecting and managing an uncorrectable error in a non-volatile memory of a microcontroller, the microcontroller having a read interface, an...
2018/0246786 RESUMING APPLICATIONS USING PASS-THROUGH SERVERS AND TRACE DATA
Aspects include receiving, at a pass-through server executing in a replay mode, a request directed to a backend resource. The request is received from an...
2018/0246785 USING GEOGRAPHICAL LOCATION INFORMATION TO PROVISION MULTIPLE TARGET STORAGES FOR A SOURCE DEVICE
Provided are a computer program product, system, and method for using geographical location information to provision multiple target storages for a source...
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