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Patent # Description
2018/0254378 Method for Producing an Optoelectronic Semiconductor Component and Optoelectronic Semiconductor Component
A method for fabricating an optoelectronic semiconductor component is disclosed. A semiconductor chip is produced by singularizing a wafer. The semiconductor...
2018/0254377 GROUP III NITRIDE BASED LED STRUCTURES INCLUDING MULTIPLE QUANTUM WELLS WITH BARRIER-WELL UNIT INTERFACE LAYERS
Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include III nitride interface layers....
2018/0254376 SYSTEMS AND METHODS FOR PREPARING GaN AND RELATED MATERIALS FOR MICRO ASSEMBLY
The disclosed technology relates generally to a method and system for micro assembling GaN materials and devices to form displays and lighting components that...
2018/0254375 METHOD FOR MANUFACTURING CRYSTALLINE SILICON-BASED SOLAR CELL AND METHOD FOR MANUFACTURING CRYSTALLINE...
A method for manufacturing a crystalline silicon-based solar cell includes forming a first intrinsic silicon-based thin-film on a first principal surface and a...
2018/0254374 PHOTODIODE STRUCTURES
Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further...
2018/0254373 PROCESS OF FORMING LIGHT-RECEIVING DEVICE
A process of forming a light-receiving device type of avalanche photodiode (APD) is disclosed. The process includes steps of: (1) growing semiconductor layers...
2018/0254372 METHOD FOR ENHANCING THE EFFICIENCY OF A SOLAR MODULE BY SUBJECTING IT TO EXTREMELY-LOW-FREQENCY EMR
The present invention provides a method for enhancing the efficiency of a photovoltaic module by subjecting it to extremely-low-frequency (ELF) electromagnetic...
2018/0254371 PHOTODETECTOR
An UV photodetector includes: a substrate, a template layer formed on the substrate, an intrinsic AlGaN layer formed on the template layer, a first n-type...
2018/0254370 PHOTODIODE WITH DECREASED DARK CURRENT AND METHOD FOR MANUFACTURING THE SAME
A photodiode having a reduced dark current includes a semiconductor layer, a first contact part, a second contact part, and an active region. The first contact...
2018/0254368 SYSTEM AND METHOD FOR MANAGING DISTRIBUTED RENEWABLE ENERGY SYSTEMS AND SERVICE PROVIDERS
A method for managing distributed renewable energy systems comprising receiving first meter data for a plurality of first meters, each of the plurality of...
2018/0254367 SOLAR CELL ASSEMBLY
A solar cell assembly comprises a first assembly of at least one photovoltaic cell and a protective glass positioned on the active face of the first assembly,...
2018/0254366 SOLAR ARRAY MODULE SYSTEM WITH PASSIVE SWITCHING
A solar array module system for generating electric-power, preconfigured to prevent electric blockage of the module when a physical row of solar cells...
2018/0254365 THIN FILM TYPE SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME
The present invention provides a thin film type solar cell and a method of manufacturing the same, the thin film type solar cell including: a substrate; a...
2018/0254364 METHOD OF RECYCLING SOLAR CELL MODULE
A method of recycling a solar cell module includes an enclosing layer that encloses a solar cell therein, a light-receiving surface layer laminated on one...
2018/0254363 SEMICONDUCTOR DEVICES HAVING MATRIX-EMBEDDED NANO-STRUCTURED MATERIALS
A structure having a bulk crystalline matrix material and a plurality of nanoscale crystallites embedded within the bulk crystalline matrix material. The bulk...
2018/0254362 MIXED TIN AND GERMANIUM PEROVSKITES
Perovskite materials useful in the manufacture of photovoltaic cells are provided. The perovskite materials have the formula AB'.sub.0.5B''.sub.0.5X.sub.3 or ...
2018/0254361 EMBEDDED JUNCTION IN HETERO-STRUCTURED BACK-SURFACE FIELD FOR PHOTOVOLTAIC DEVICES
A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field...
2018/0254360 METALLIZATION OF SOLAR CELLS
Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves...
2018/0254359 SOLAR CELL AND SOLAR CELL MANUFACTURING METHOD
A solar cell includes an n-type semiconductor substrate having a p-n junction and a back-surface side impurity-diffusion layer. The back-surface side...
2018/0254358 SOLAR CELL MODULE MANUFACTURING METHOD
A solar cell module manufacturing method is provided. This method includes: arranging a printing plate over a solar cell element in proximity to a surface of...
2018/0254357 DISTRIBUTED BRAGG REFLECTOR STRUCTURES IN MULTIJUNCTION SOLAR CELLS
A multijunction solar cell and its method of fabrication, including an upper and a lower solar subcell each having an emitter layer and a base layer forming a...
2018/0254356 DIAMOND-BACKED PHOTODIODES, DIAMOND-SANDWICHED PHOTODIODES, PHOTODIODE SYSTEMS AND RELATED METHODS OF MANUFACTURE
A photodiode device and method of manufacturing the same are disclosed. A stack of functional layers of the photodiode device, formed of crystalline...
2018/0254355 HIGH WITHSTAND VOLTAGE SCHOTTKY BARRIER DIODE
A high withstand voltage Schottky barrier diode includes a first layer that includes a first Ga.sub.2O.sub.3-based single crystal including a first Group IV...
2018/0254354 SILICON CARBIDE SEMICONDUCTOR DEVICE
A mesa type p-n junction diode silicon carbide semiconductor device that includes a first silicon carbide semiconductor substrate, a first drift layer formed...
2018/0254353 INTEGRATED FUSE DEVICE
A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device...
2018/0254352 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device with favorable electrical characteristics is to be provided. A highly reliable semiconductor device is to be provided. A semiconductor...
2018/0254351 LOGIC CIRCUITRY USING THREE DIMENSIONALLY STACKED DUAL-GATE THIN-FILM TRANSISTORS
Disclosed is a logic circuit using three-dimensionally stacked dual-gate thin-film transistors, including a substrate, a first dual-gate thin-film transistor...
2018/0254350 UNIPOLAR COMPLEMENTARY LOGIC
A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field...
2018/0254349 MANUFACTURING METHODS OF OXIDE THIN FILM TRANSISTORS
The manufacturing method of oxide thin film transistors (TFTs) includes: providing a substrate and forming an oxide semiconductor active layer on the...
2018/0254348 Stacked Gate-All-Around FinFET and Method Forming the Same
A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the...
2018/0254347 SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURE WITH TWO CHANNEL LAYERS AND MANUFACTURING METHOD THEREOF
A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to...
2018/0254346 SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF
A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes...
2018/0254345 STRAINED SEMICONDUCTOR NANOWIRE
At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator...
2018/0254344 VERTICAL TRANSISTOR WITH REDUCED GATE-INDUCED-DRAIN-LEAKAGE CURRENT
A method of forming a vertical transport fin field effect transistor, including, forming a bottom source/drain layer at the surface of the substrate, forming...
2018/0254343 METHOD OF FORMING A SEMICONDUCTOR DEVICE
A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a...
2018/0254342 METHOD FOR FORMING A LATERAL SUPER-JUNCTION MOSFET DEVICE AND TERMINATION STRUCTURE
A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column...
2018/0254341 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second...
2018/0254340 TUNNEL FINFET WITH SELF-ALIGNED GATE
Structures and methods for a tunnel field-effect transistor (TFET). The TFET includes a gate electrode, a source region having a first conductivity type, a...
2018/0254339 SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR DEVICE, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE
A semiconductor epitaxial wafer includes a semiconductor wafer, and a semiconductor layer of a first conductivity type disposed on a main surface of the...
2018/0254338 Semiconductor Device
A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the...
2018/0254337 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor layer. A second semiconductor layer is disposed on the first semiconductor layer. A structure layer is...
2018/0254336 INSULATED GATE TURN-OFF DEVICE HAVING LOW CAPACITANCE AND LOW SATURATION CURRENT
An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N- epi layer, a P-well,...
2018/0254335 TUNNEL FIELD EFFECT TRANSISTOR HAVING ANISOTROPIC EFFECTIVE MASS CHANNEL
A tunnel field effect transistor (TFET) device is disclosed. The TFET includes a substrate, heavily doped source and drain regions disposed at opposite ends of...
2018/0254334 Methods Of Forming NAND Cell Units And NAND Cell Units
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
2018/0254333 FORMING A FIN USING DOUBLE TRENCH EPITAXY
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy....
2018/0254332 HIGH-ELECTRON-MOBILITY TRANSISTORS WITH COUNTER-DOPED DOPANT DIFFUSION BARRIER
III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A...
2018/0254331 ETCH-RESISTANT SPACER FORMATION ON GATE STRUCTURE
The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include:...
2018/0254330 REPLACEMENT METAL GATE SCHEME WITH SELF-ALIGNMENT GATE FOR VERTICAL FIELD EFFECT TRANSISTORS
A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin...
2018/0254329 NANOSHEET MOSFET WITH PARTIAL RELEASE AND SOURCE/DRAIN EPITAXY
A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a ...
2018/0254328 THIN FILM TRANSISTOR, DISPLAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME, AND FABRICATING METHOD THEREOF
The present application discloses a thin film transistor, a display substrate and display panel having the same, and a fabricating method thereof. The thin...
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