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Patent # Description
2018/0308833 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a metal substrate, an insulating substrate, a first bonding member,...
2018/0308832 MICRO LED DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
The present invention relates to a puzzle-type micro light emitting diode (LED) display device which is capable of implementing a display having various sizes,...
2018/0308831 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a...
2018/0308830 Semiconductor Devices for Integration with Light Emitting Chips and Modules Thereof
A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost...
2018/0308829 Stacked Electronic Structure
A stacked electronic structure comprises: a substrate and a magnetic device, wherein a plurality of electronic devices and a plurality of conductive pillars...
2018/0308828 Semiconductor Device and Method of Manufacture
A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package...
2018/0308827 Power Semiconductor Arrangement Having a Stack of Connection Plates
A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the...
2018/0308826 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes: a first semiconductor die and a second semiconductor die connected on the first semiconductor die, in which the first...
2018/0308825 METHOD FOR FORMING CHIP PACKAGE STRUCTURE WITH ADHESIVE LAYER
A method for forming a chip package structure is provided. The method includes forming a chip on an adhesive layer. The chip has a front surface and a back...
2018/0308824 Semiconductor Device with Discrete Blocks
A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having...
2018/0308823 STACKED SEMICONDUCTOR STRUCTURE
A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a...
2018/0308822 METHODS AND APPARATUS FOR SEMICONDUCTOR PACKAGE PROCESSING
A fan-out process using chemical mechanical planarization (CMP) reduces the step-height between a semiconductor die and the surrounding overmolding of a...
2018/0308821 SEMICONDUCTOR WIRE BONDING MACHINE CLEANING DEVICE AND METHOD
A methodology and medium for regular and predictable cleaning the support hardware such as capillary tube in semiconductor assembly equipment components, while...
2018/0308820 MULTI-LAYERED COMPOSITE BONDING MATERIALS AND POWER ELECTRONICS ASSEMBLIES INCORPORATING THE SAME
A multilayer composite bonding material for transient liquid phase bonding a semiconductor device to a metal substrate includes thermal stress compensation...
2018/0308819 Die Processing
Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to...
2018/0308818 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
A semiconductor structure and a method for forming the same are provided. The method includes: providing a first semiconductor workpiece; depositing a first...
2018/0308817 MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
A method for forming a semiconductor structure includes: providing a semiconductor substrate having a first pad and a second pad on a top surface of the...
2018/0308816 ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING
An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated...
2018/0308815 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
2018/0308814 SEMICONDUCTOR DEVICE
A semiconductor device may include a semiconductor substrate, a first bonding pad provided on an upper surface of the semiconductor substrate and constituted...
2018/0308813 3D-INTERCONNECT
A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a...
2018/0308812 SEMICONDUCTOR DEVICE
A semiconductor device may include a semiconductor substrate, a first bonding pad provided on an upper surface of the semiconductor substrate and constituted...
2018/0308811 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device comprises a die, a dielectric layer, a plurality of conductive pillars and a package body. The die has an active surface, a back...
2018/0308810 DEVICES AND METHODS RELATED TO ELECTROSTATIC DISCHARGE PROTECTION BENIGN TO RADIO-FREQUENCY OPERATION
Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and...
2018/0308809 DISCHARGING BRUSH, DISCHARGING DEVICE, AND DISCHARGING METHOD
The discharging brush 1 includes a conductive brush unit 11 and a grounding wire 15 connecting the brush unit 11 with a grounding point via a resistor 14. In a...
2018/0308808 ACTIVE SHIELD FOR PROTECTING A DEVICE FROM BACKSIDE ATTACKS
An electronic apparatus includes, a substrate, one or more routing layers, and an active shield layer. The substrate includes active devices. The routing...
2018/0308807 CHIP SECURITY FINGERPRINT
Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification "fingerprint" layer. A semiconductor chip...
2018/0308806 CHIP SECURITY FINGERPRINT
Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification "fingerprint" layer. A semiconductor chip...
2018/0308805 PACKAGE ASSEMBLY FOR EMBEDDED DIE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS
Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment,...
2018/0308804 DEVICE HAVING SUBSTRATE WITH CONDUCTIVE PILLARS
A device includes a substrate that includes conductive structures and has a first surface that is opposite to a second surface. Conductive pillars are built up...
2018/0308803 SEMICONDUCTOR STRUCTURE
A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and...
2018/0308802 OXIDATION RESISTANT BARRIER METAL PROCESS FOR SEMICONDUCTOR DEVICES
An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the...
2018/0308801 SEMICONDUCTOR DEVICE HAVING AN EXTRA LOW-K DIELECTRIC LAYER AND METHOD OF FORMING THE SAME
A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric...
2018/0308800 PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an...
2018/0308799 FLEXIBLE ELECTRONIC CIRCUITS WITH EMBEDDED INTEGRATED CIRCUIT DIE AND METHODS OF MAKING AND USING THE SAME
Flexible integrated circuit (IC) modules, flexible IC devices, and methods of making and using flexible IC modules are presented herein. A flexible integrated...
2018/0308798 SPLIT RAIL STRUCTURES LOCATED IN ADJACENT METAL LAYERS
A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that...
2018/0308797 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, an inter-layer dielectric layer, a contact plug, and a contact hole liner. The substrate has a source/drain...
2018/0308796 Metal Patterning For Internal Cell Routing
A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first...
2018/0308795 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a...
2018/0308794 SEMICONDUCTOR DEVICE
A semiconductor apparatus includes a semiconductor device having a semiconductor circuit formed on a first main surface, and including a via having an opening...
2018/0308793 STRUCTURE AND FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE
Structures and formation methods of a semiconductor device structure are provided. A method includes depositing a first layer including Al atoms to cover a...
2018/0308792 THIN ELECTRONIC PACKAGE ELEMENTS USING LASER SPALLATION
Discussed generally herein are methods and devices for flexible fabrics or that otherwise include thin traces. A device can include a flexible polyimide...
2018/0308791 THIN RECON INTERPOSER PACKAGE WITHOUT TSV FOR FINE INPUT/OUTPUT PITCH FAN-OUT
Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active...
2018/0308790 SEMICONDUCTOR MODULE
A semiconductor module may include a semiconductor chip; a first electrode body; and a second electrode body; wherein the semiconductor chip may include a...
2018/0308789 PACKAGING STRUCTURE, ELECTRONIC DEVICE, AND PACKAGING METHOD
The invention discloses a packaging structure, including a substrate, a fan-out unit, and a wiring layer. The fan-out unit includes a first chip and a second...
2018/0308788 SEMICONDUCTOR DEVICE WITH THROUGH-MOLD VIA
In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device...
2018/0308787 SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has at least one chip, through...
2018/0308786 Liquid-Cooled Heat Sink
A liquid-cooled heat sink includes a heat absorption module having a liquid storage container with one heat conductive side, a liquid inlet and a liquid; a...
2018/0308785 METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a...
2018/0308784 STACKED DIE PACKAGE WITH THROUGH-MOLD THERMALLY CONDUCTIVE STRUCTURES BETWEEN A BOTTOM DIE AND A THERMALLY...
An apparatus is described that includes a first semiconductor die. A second semiconductor die is stacked on the first semiconductor die. The first...
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