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Patent # Description
2018/0308783 DYNAMIC MOUNTING THERMAL MANAGEMENT FOR DEVICES ON BOARD
Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a...
2018/0308782 THERMAL INTERFACE MATERIAL STRUCTURES INCLUDING PROTRUDING SURFACE FEATURES TO REDUCE THERMAL INTERFACE...
A process of forming a thermal interface material structure includes forming an assembly that includes a thermal interface material disposed between a first...
2018/0308781 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a...
2018/0308780 THERMALLY SUPERCONDUCTING HEAT DISSIPATION DEVICE AND MANUFACTURING METHOD THEREOF
A thermally superconducting radiator and a method for manufacturing the same. The thermally superconducting radiator comprises a plurality of separators and a...
2018/0308779 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding...
2018/0308778 Integrated Circuit Packages and Methods for Forming the Same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector...
2018/0308777 ELECTRONIC COMPONENT MOUNTING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC MODULE
An electronic component mounting board reduces shadows produced along its perimeter to improve the mountability of an electronic device and an electronic...
2018/0308776 ELECTROMAGNETIC SHIELD STRUCTURE OF HIGH FREQUENCY CIRCUIT AND HIGH FREQUENCY MODULE
A recess in a metal housing accommodating a high frequency package includes a first space and a second space and has a winners podium shape in cross-sectional...
2018/0308775 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
In a semiconductor device, when a printed circuit board is pressed against a bottom part of a case with an adhesive interposed therebetween, the back surface...
2018/0308774 SCAN TESTABLE THROUGH SILICON VIAs
The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of...
2018/0308773 METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM...
A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer...
2018/0308772 TRANSISTOR WORK FUNCTION ADJUSTMENT BY LASER STIMULATION
Methods and apparatuses for modifying a work function of transistors included in an integrated circuit are disclosed. A tester unit may be configured to test...
2018/0308771 PROTON RADIATION AS A TOOL FOR SELECTIVE DEGRADATION AND PHYSICS BASED DEVICE MODEL TEST AND CALIBRATION
A method of evaluating localized degradation of a III-V compound semiconductor. The method includes preparing first and second III-V compound semiconductors....
2018/0308770 SUBSTRATE BONDING APPARATUS AND SUBSTRATE BONDING METHOD
To improve the throughput of substrate bonding. A substrate bonding apparatus that bonds first and second substrates so that contact regions in which the first...
2018/0308769 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a first source/drain feature, a second source/drain feature and a dielectric plug. The substrate has a...
2018/0308768 GATE METAL PATTERNING FOR TIGHT PITCH APPLICATIONS
Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical...
2018/0308767 GATE METAL PATTERNING FOR TIGHT PITCH APPLICATIONS
Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical...
2018/0308766 GATE METAL PATTERNING FOR TIGHT PITCH APPLICATIONS
Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical...
2018/0308764 VERTICAL SILICON/SILICON-GERMANIUM TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGES
A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins...
2018/0308763 VERTICAL SILICON/SILICON-GERMANIUM TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGES
A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins...
2018/0308762 3D VERTICAL FET WITH TOP AND BOTTOM GATE CONTACTS
A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical...
2018/0308761 Contact Structure and Method of Fabricating the Same
An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common...
2018/0308760 Forming a Protective Layer to Prevent Formation of Leakage Paths
A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask...
2018/0308759 METHODS OF FORMING A CT PILLAR BETWEEN GATE STRUCTURES IN A SEMICONDUCTOR
A method includes providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate. A CT pillar layer is...
2018/0308758 Methods of Forming Sources and Drains for FinFETs Using Solid Phase Epitaxy With Laser Annealing
Methods disclosed herein include replacing top portions of source and drain sections of a finFET structure having sidewalls and a first doping with doped...
2018/0308757 SEMICONDUCTOR DEVICE
A semiconductor device includes: reverse conducting switching elements-in each of which a diode element and a switching element are arranged in parallel on a...
2018/0308756 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A semiconductor package has a semiconductor chip on a wiring board, sealed with a sealant. A semiconductor package substrate is formed with V grooves along...
2018/0308755 DEVICE CHIP MANUFACTURING METHOD
A device chip manufacturing method includes a passivation film removing step of removing a passivation film along each division line, a wafer dividing step of...
2018/0308754 GRID SELF-ALIGNED METAL VIA PROCESSING SCHEMES FOR BACK END OF LINE (BEOL) INTERCONNECTS AND STRUCTURES...
Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect...
2018/0308753 Process Integration Techniques Using A Carbon Layer To Form Self-Aligned Structures
Process integration techniques are disclosed that use a carbon fill layer during formation of self-aligned structures. A carbon layer may be placed over an...
2018/0308752 MIDDLE-OF-LINE LOCAL INTERCONNECT STRUCTURES WITH HYBRID FEATURES
Interconnect structures and methods of forming interconnect structures. An opening is formed that penetrates from a top surface of a dielectric layer into the...
2018/0308751 Methods for Forming Contact Plugs with Reduced Corrosion
A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact...
2018/0308750 FIELD EFFECT DEVICE WITH REDUCED CAPACITANCE AND RESISTANCE IN SOURCE/DRAIN CONTACTS AT REDUCED GATE PITCH
A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region...
2018/0308749 MULTI-METAL FILL WITH SELF-ALIGN PATTERNING
The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap...
2018/0308748 3D STACKING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A 3D stacking semiconductor device and a manufacturing method thereof are provided. The method includes using a set of N etch masks for creating O different...
2018/0308747 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device is provided. The method comprises arranging an insulator, forming a hole in the insulator, first exposing for...
2018/0308746 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
Semiconductor structure and fabrication method are provided. The method includes: providing a substrate including device regions and isolation regions,...
2018/0308745 TRENCH ISOLATED IC WITH TRANSISTORS HAVING LOCOS GATE DIELECTRIC
An electronic device includes an isolated region surrounded by an isolation ring over a semiconductor substrate. A well of a first conductivity type is located...
2018/0308744 AMORPHOUS METAL THIN FILM NONLINEAR RESISTOR
Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors....
2018/0308743 FABRICATION OF VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS WITH A SELF-ALIGNED SEPARATOR AND AN ISOLATION...
A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region...
2018/0308742 FABRICATION OF VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS WITH A SELF-ALIGNED SEPARATOR AND AN ISOLATION...
A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region...
2018/0308741 CONFIGURABLE HIGH TEMPERATURE CHUCK FOR USE IN A SEMICONDUCTOR WAFER PROCESSING SYSTEM
A reconfigurable wafer spin chuck for supporting a wafer includes a rotatable chuck base having a first opening formed therein and including one or more...
2018/0308740 SUBSTRATE TABLE AND LITHOGRAPHIC APPARATUS
A substrate table to support a substrate, the substrate table including a main body, burls extending from the main body and having first upper ends that define...
2018/0308739 ADHESIVE TAPE FOR SEMICONDUCTOR PROCESSING AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
The pressure sensitive adhesive tape for semiconductor processing of the present invention is a pressure sensitive adhesive tape for semiconductor processing,...
2018/0308738 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE REMOVING METHOD
A substrate processing apparatus is provided. The substrate processing apparatus includes: an electro-static chuck configured to retain a substrate on a...
2018/0308737 ELECTROSTATIC CHUCK DEVICE
An electrostatic chuck device comprising: a placing table having a placing surface on which a plate-shaped sample is placed, an electrostatic attraction...
2018/0308736 Electrostatic Chuck Assembly Having A Dielectric Filler
Embodiments include an electrostatic chuck assembly having an electrostatic chuck mounted on an insulator. The electrostatic chuck and insulator may be within...
2018/0308735 SEMICONDUCTOR PROCESS EQUIPMENT
A system for processing a substrate is provided including a first planar motor, a substrate carrier, a first processing chamber, and a first lift. The first...
2018/0308734 PACKAGE ASSEMBLY FOR THIN WAFER SHIPPING AND METHOD OF USE
A package assembly for thin wafer shipping using a wafer container and a method of use are disclosed. The package assembly includes a shipping container and a...
2018/0308733 GAS PURGE FILTER
Disclosed is a gas purge filter used in a housing container provided with a container main body and a lid body. The gas purge filter has a filter housing...
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