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Patent # Description
2018/0323234 ELECTRODELESS LIGHT-EMITTING DIODE DISPLAY AND METHOD FOR FABRICATING THE SAME
An electrodeless LED display and a method for fabricating the same are disclosed. In the method, an epitaxial layer is provided and a transparent conduction...
2018/0323233 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode...
2018/0323232 SOLID-STATE IMAGING DEVICE
A solid-state imaging device includes a plurality of pixels two-dimensionally arranged on a semiconductor substrate. Each of the pixels includes at least one...
2018/0323231 SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS
A solid-state imaging device has a first substrate, a second substrate, and a third substrate. The first substrate has a plurality of first photoelectric...
2018/0323230 SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS
A solid-state imaging device including an imaging area where a plurality of unit pixels are disposed to capture a color image, wherein each of the unit pixels...
2018/0323229 READOUT ARCHITECTURE FOR EVENT-DRIVEN PIXELS
Methods and systems for reading out a pixel array are provided. An example system may include a plurality of pixels. The system may further include an...
2018/0323228 IMAGE SENSOR
An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the...
2018/0323227 WAFER LEVEL PACKAGING METHOD
A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is...
2018/0323226 METHOD AND APPARATUS FOR BACKSIDE ILLUMINATION SENSOR
A semiconductor device includes a device substrate having a dielectric layer and a metal wire in the dielectric layer, a first opening on the metal wire and...
2018/0323225 SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, AND ELECTRONIC APPARATUS
A solid-state imaging device according to the present disclosure includes a pixel array unit in which unit pixels including photoelectric conversion elements...
2018/0323224 METHOD FOR FORMING PIXEL STRUCTURE
A method for forming a pixel structure is provided. The method includes: forming a gate electrode layer on a substrate; forming a first insulating layer on the...
2018/0323223 DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for producing a display device includes locating a substrate, including a plurality of pixels, on a jig including a magnet; locating a plate formed of...
2018/0323222 TRANSISTOR SUBSTRATE AND DISPLAY DEVICE
In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied...
2018/0323221 METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on...
2018/0323220 METAL OXIDE FILM AND METHOD FOR FORMING METAL OXIDE FILM
A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10...
2018/0323219 ACTIVE DEVICE ARRAY STRUCTURE
An active device array structure including a substrate including a first region and a second region, and first signal lines, second signal lines, third signal...
2018/0323218 TFT ARRAY SUBSTRATE
A TFT array substrate includes a display zone having data lines, scan lines, and sub-pixels arranged in an array. For the sub-pixels of the same row, each of...
2018/0323217 DISTRIBUTION OF TFT COMPONENTS IN LTPS PROCESS
Disclosed is a distribution of TFT components in the LTPS process. A pair of parallel data lines are arranged between an i.sup.th and (i+1).sup.th rows of...
2018/0323216 DISPLAY SUBSTRATE, FABRICATING METHOD THEREOF, AND DISPLAY APPARATUS
The present disclosure provides a display substrate, a fabricating method thereof, and a display apparatus including the display substrate. The display...
2018/0323215 Inverter Circuitry
Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first...
2018/0323214 Vertical Ferroelectric Field Effect Transistor Constructions, Constructions Comprising A Pair Of Vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
2018/0323213 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers...
2018/0323212 Memory Arrays, and Methods of Forming Memory Arrays
Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends...
2018/0323211 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer;...
2018/0323210 SEMICONDUCTOR DEVICE
According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first...
2018/0323209 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES
A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor...
2018/0323208 VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE
A method of forming a vertical non-volatile (NV) memory device such as 3-D NAND flash memory includes forming a vertical NV memory cell string within an...
2018/0323207 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a...
2018/0323206 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME
A semiconductor device includes interlayer insulating layers and conductive patterns alternately stacked over a pipe gate, a first slit and a second slit...
2018/0323204 SEMICONDUCTOR MEMORY DEVICE
A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and...
2018/0323203 MULTIPLE-BIT ELECTRICAL FUSES
A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a...
2018/0323202 MULTIPLE-BIT ELECTRICAL FUSES
A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a...
2018/0323201 STATIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF
An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down...
2018/0323200 Memory Arrays
A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a...
2018/0323199 Memory Arrays
A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising...
2018/0323198 Thyristor Memory Cell with Assist Device
A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located...
2018/0323197 Thyristor Volatile Random Access Memory and Methods of Manufacture
Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. An operation is...
2018/0323196 METHOD AND CIRCUIT FOR INTEGRATED CIRCUIT BODY BIASING
The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices...
2018/0323195 STACKED CHANNEL STRUCTURES FOR MOSFETS
Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing...
2018/0323194 PRESERVING CHANNEL STRAIN IN FIN CUTS
A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET...
2018/0323193 PRESERVING CHANNEL STRAIN IN FIN CUTS
A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET...
2018/0323192 SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF
A method for fabricating a semiconductor structure includes providing a substrate including isolation regions and a device region between adjacent isolation...
2018/0323191 FIN-TYPE FIELD EFFECT TRANSISTORS WITH SINGLE-DIFFUSION BREAKS AND METHOD
Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation...
2018/0323190 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow...
2018/0323189 Field-Effect Semiconductor Device Having a Heterojunction Contact
According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body...
2018/0323188 INDIRECT READOUT FET
A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed...
2018/0323187 Substrate Isolation For Low-Loss Radio Frequency (RF) Circuits
Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions...
2018/0323186 Linearity and Lateral Isolation in a BiCMOS Process Through Counter-Doping Of Epitaxial Silicon Region
Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type...
2018/0323185 DIODE-TRIGGERED SCHOTTKY SILICON-CONTROLLED RECTIFIER FOR FIN-FET ELECTROSTATIC DISCHARGE CONTROL
Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a...
2018/0323184 High Voltage Electrostatic Discharge (ESD) Protection
Methods, circuits, devices, and systems for high voltage electrostatic discharge (ESD) protection are provided. An example ESD protection device includes: a...
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