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Patent # Description
2018/0323183 Electrostatic Discharge Protection Device
An electrostatic discharge protection device includes: a semiconductor substrate; an N-type doped well on the substrate, the N-type doped well including a...
2018/0323182 SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM
A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the...
2018/0323181 LIGHT-EMITTING APPARATUS AND FABRICATING METHOD THEREOF
A fabricating method of a light-emitting apparatus including the following steps is provided. An adhesive layer having first adhesive bump groups including...
2018/0323180 MATRIX-ADDRESSED TILES AND ARRAYS
A matrix-addressed tile comprises a tile substrate having a two-dimensional array of pixels arranged in rows and columns defining a contiguous pixel area that...
2018/0323179 MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
2018/0323178 STRUCTURES AND METHODS FOR ELECTRICAL CONNECTION OF MICRO-DEVICES AND SUBSTRATES
An exemplary micro-device and substrate structure includes a destination substrate and one or more contact pads disposed thereon, a micro-device disposed on or...
2018/0323177 3DIC Formation with Dies Bonded to Formed RDLs
A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level...
2018/0323176 SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips...
2018/0323175 SEMICONDUCTOR MODULE
A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the...
2018/0323174 FABRICATION AND USE OF THROUGH SILICON VIAS ON DOUBLE SIDED INTERCONNECT DEVICE
An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device...
2018/0323173 CONNECTION PADS FOR LOW CROSS-TALK VERTICAL WIREBONDS
Wirebond bondpads on semiconductor packages that result in reduced cross-talk and/or interference between vertical wires are disclosed. The vertical wirebonds...
2018/0323172 ELIMINATING DIE SHADOW EFFECTS BY DUMMY DIE BEAMS FOR SOLDER JOINT RELIABILITY IMPROVEMENT
A package with improved solder joint reliability is disclosed. The package includes dummy beams with less rigidity and stiffness (relative to the die) that are...
2018/0323171 DEFORMABLE CLOSED-LOOP MULTI-LAYERED MICROELECTRONIC DEVICE
A deformable closed-loop multi-layered microelectronic device is provided. A top layer, a bottom layer and a middle layer of the microelectronic device each...
2018/0323170 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a...
2018/0323169 DUAL-SIDED MEMORY MODULE WITH CHANNELS ALIGNED IN OPPOSITION
Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit...
2018/0323168 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an...
2018/0323167 METHODS OF OPERATING A WIRE BONDING MACHINE TO IMPROVE CLAMPING OF A SUBSTRATE, AND WIRE BONDING MACHINES
A method of operating a wire bonding machine is provided. The method includes the steps of: (a) supporting a substrate on a material handling system of the...
2018/0323166 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
The disclosure includes: a first lifting step for bonding a wire at a first position (13) with a capillary and for lifting the capillary up to a first height...
2018/0323165 VERTICALLY DIE-STACKED BONDER AND METHOD USING THE SAME
A vertically die-stacked bonder able to stack laterally dies one by one includes a self-elevating unit, a retrieval unit neighbored to the self-elevating unit,...
2018/0323164 SEMI-CONDUCTOR PACKAGE STRUCTURE
Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts,...
2018/0323163 Protrusion Bump Pads for Bond-on-Trace Processing
An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion...
2018/0323162 SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES
An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include...
2018/0323161 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of...
2018/0323160 METHODS OF FORMING AND OPERATING SEMICONDUCTOR DEVICES INCLUDING DUMMY CHIPS
A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first...
2018/0323159 MICROELECTRONIC DEVICES DESIGNED WITH HIGH FREQUENCY COMMUNICATION DEVICES INCLUDING COMPOUND SEMICONDUCTOR...
Embodiments of the invention include a microelectronic device that includes an overmolded component having a first die with a silicon based substrate. A second...
2018/0323158 MAGNETIC INDUCTOR STACK INCLUDING INSULATING MATERIAL HAVING MULTIPLE THICKNESSES
Provided is an inductor structure. In embodiments of the invention, the inductor structure includes a laminated first stack and a laminated second stack. The...
2018/0323157 SECURITY ARRANGEMENT FOR INTEGRATED CIRCUITS USING MICROCAPSULES IN DIELECTRIC LAYER
An apparatus comprises a plurality of conductive elements arranged within at least a first conductive layer and a dielectric layer comprising a plurality of...
2018/0323156 BREAKABLE SUBSTRATE FOR SEMICONDUCTOR DIE
In some examples, a device includes a substrate and a conductive pad extending through the substrate, wherein the substrate is coupled to the conductive pad at...
2018/0323155 TRENCH MOSFET DEVICE AND THE PREPARATION METHOD THEREOF
A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. A semiconductor substrate of a first...
2018/0323154 ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF
An electronic device includes a first semiconductor die, a plurality of bumps, and a substrate. The first semiconductor die includes a first conductive...
2018/0323153 SEMICONDUCTOR DEVICE AND METHOD OF FORMING BACKSIDE OPENINGS FOR AN ULTRA-THIN SEMICONDUCTOR DIE
A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with...
2018/0323152 SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at...
2018/0323151 WET ETCH REMOVAL OF Ru SELECTIVE TO OTHER METALS
A method for forming a conductive structure for a semiconductor device includes depositing a barrier layer in a trench formed in a dielectric material and...
2018/0323150 Multi-Stacked Package-on-Package Structures
A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the...
2018/0323149 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating...
2018/0323148 SEMICONDUCTOR DEVICE AND IO-CELL
According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines...
2018/0323147 3D INTERCONNECT MULTI-DIE INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV)...
2018/0323146 MULTI-DIE INDUCTORS WITH COUPLED THROUGH-SUBSTRATE VIA CORES
A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least ...
2018/0323145 3D INTERCONNECT MULTI-DIE INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV)...
2018/0323144 MULTI-DIE INDUCTORS WITH COUPLED THROUGH-SUBSTRATE VIA CORES
A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least ...
2018/0323143 PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME
A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including...
2018/0323142 Structure Of Integrated Circuitry And A Method Of Forming A Conductive Via
A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically...
2018/0323141 LOW-DISPERSION COMPONENT IN AN ELECTRONIC CHIP
A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components...
2018/0323140 ELECTRONIC DEVICE WITH DELAMINATION RESISTANT WIRING BOARD
This invention provides an electronic device with improved reliability. The electronic device has a wiring board with a back-surface ground pattern formed at...
2018/0323139 METHOD FOR MANUFACTURING A DEVICE WITH INTEGRATED-CIRCUIT CHIP BY DIRECT DEPOSIT OF CONDUCTIVE MATERIAL
The invention relates to a method for manufacturing a device with a secure integrated-circuit chip, said device having an insulating substrate, electrically...
2018/0323138 REDUNDANT THROUGH-HOLE INTERCONNECT STRUCTURES
Techniques and mechanisms for efficiently providing reliable connection through a substrate such as that of a core of a packaged integrated circuit device. In...
2018/0323137 INTEGRATED CIRCUIT (IC) PACKAGE AND PACKAGE SUBSTRATE COMPRISING STACKED VIAS
A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates...
2018/0323136 CHIP PACKAGE WITH SIDEWALL METALLIZATION
A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench...
2018/0323135 Method And System For Improved Matching For On-Chip Capacitors
Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers....
2018/0323134 ELECTRIC CONDUCTOR TRACK, METHOD, AND USE
A conductor track which is designed in particular for use with ultrasonic welding. The invention also relates to an associated method and to an associated use.
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