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Patent # Description
2018/0323133 SEMICONDUCTOR DEVICES WITH BACK-SIDE COILS FOR WIRELESS SIGNAL AND POWER COUPLING
A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped...
2018/0323132 DISTRIBUTION AND STABILIZATION OF FLUID FLOW FOR INTERLAYER CHIP COOLING
A method of forming metallic pillars between a fluid inlet and outlet for two-phase fluid cooling. The method may include; forming an arrangement of metallic...
2018/0323131 POWER ELECTRONICS ASSEMBLIES HAVING A SEMICONDUCTOR COOLING CHIP AND AN INTEGRATED FLUID CHANNEL SYSTEM
A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled...
2018/0323130 ADHESIVE POLYMER THERMAL INTERFACE MATERIAL WITH SINTERED FILLERS FOR THERMAL CONDUCTIVITY IN MICRO-ELECTRONIC...
An adhesive polymer thermal interface material is described with sintered fillers for thermal conductivity in micro-electronic packaging. Embodiments include a...
2018/0323129 SEMICONDUCTOR PACKAGE HAVING ROUTABLE ENCAPSULATED CONDUCTIVE SUBSTRATE AND METHOD
A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame...
2018/0323128 SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING
Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may...
2018/0323127 STACKED FAN-OUT PACKAGE STRUCTURE
A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A...
2018/0323126 PACKAGE STRUCTURE
The present disclosure provides a package structure including a redistribution layer and a die. The redistribution layer includes a switch circuit portion and...
2018/0323125 ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME
In an electronic device, an inner lead of a signal terminal includes a base member, and a film on a surface of the inner lead adjacent to a bonding surface....
2018/0323124 CURABLE SILICONE RESIN COMPOSITION, SILICONE RESIN COMPOSITE, PHOTOSEMICONDUCTOR LIGHT EMITTING DEVICE,...
A curable silicone resin composition is provided, including (A) a curable silicone resin-forming component of which a viscosity is 0.02 Pas or greater and 100...
2018/0323123 THIOUREA ORGANIC COMPOUND FOR GALLIUM ARSENIDE BASED OPTOELECTRONICS SURFACE PASSIVATION
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gallium arsenide substrate,a thiourea-based passivation...
2018/0323122 CERAMIC-ALUMINUM CONJUGATE, POWER MODULE SUBSTRATE, AND POWER MODULE
The present invention provides a ceramic-aluminum bonded body in which Mg-containing oxide having a spinel crystal structure are dispersed in an aluminum...
2018/0323121 Multi-Layer Substrate For Semiconductor Packaging
The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a...
2018/0323120 POWER MODULE
The power module includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface...
2018/0323119 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an...
2018/0323118 Dam for Three-Dimensional Integrated Circuit
An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled...
2018/0323117 IN-KERF TEST STRUCTURE AND TESTING METHOD FOR A MEMORY ARRAY
Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one...
2018/0323116 BOTTOM EMISSION MICROLED DISPLAY AND A REPAIR METHOD THEREOF
A bottom emission microLED display includes a microLED disposed above a transparent substrate; a light guiding layer surrounding the microLED to controllably...
2018/0323115 Bulk CMOS RF Switch With Reduced Parasitic Capacitance
Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap)...
2018/0323114 Bulk CMOS RF Switch With Reduced Parasitic Capacitance
Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap)...
2018/0323113 INTEGRATION SCHEME FOR GATE HEIGHT CONTROL AND VOID FREE RMG FILL
A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include...
2018/0323112 STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over...
2018/0323111 FORMING A HYBRID CHANNEL NANOSHEET SEMICONDUCTOR STRUCTURE
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner...
2018/0323110 HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
2018/0323109 MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS
Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a...
2018/0323108 Methods for Forming Fin Field-Effect Transistors
A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned...
2018/0323107 SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF
A method for fabricating a semiconductor structure includes forming a plurality of gate structures on the base substrate with each gate structure including a...
2018/0323106 CO-PLANAR P-CHANNEL AND N-CHANNEL GALLIUM NITRIDE-BASED TRANSISTORS ON SILICON AND TECHNIQUES FOR FORMING SAME
Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some...
2018/0323105 Simultaneous Break and Expansion System for Integrated Circuit Wafers
Improved methods and apparatuses for singulating integrated circuit (IC) dies that reduce or eliminate die collisions and work well with very small dies....
2018/0323104 TRIBLOCK COPOLYMERS FOR SELF-ALIGNING VIAS OR CONTACTS
Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures,...
2018/0323103 METHODS AND APPARATUS FOR FILLING A FEATURE DISPOSED IN A SUBSTRATE
Embodiments of methods and apparatus for filling a feature disposed in a substrate are disclosed herein. In some embodiments, a method for filling a feature...
2018/0323102 Selective Deposition of Dielectric Materials
The present disclosure relates to a method for selectively forming a dielectric material on a first area of a top surface of a substrate. In an embodiment, the...
2018/0323101 FORMING INTERCONNECTS WITH SELF-ASSEMBLED MONOLAYERS
Embodiments of the disclosure are directed to using a SAM liner to promote electroless deposition of metal for integrated circuit interconnects. The SAM liner...
2018/0323100 METAL VIA PROCESSING SCHEMES WITH VIA CRITICAL DIMENSION (CD) CONTROL FOR BACK END OF LINE (BEOL) INTERCONNECTS...
Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer...
2018/0323098 WAFER POSITIONING PEDESTAL FOR SEMICONDUCTOR PROCESSING
An assembly used in a process chamber for depositing a film on a wafer and including a pedestal extending from a central axis. An actuator is configured for...
2018/0323097 EXPANSION METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which...
2018/0323096 SYSTEMS AND METHODS FOR PASSIVE ALIGNMENT OF SEMICONDUCTOR WAFERS
An example passive wafer alignment device can include a stage for holding a wafer, a plurality of pins arranged on the stage, the pins being arranged to...
2018/0323095 IMAGE BASED SUBSTRATE MAPPER
Methods and apparatus for detecting warpage in a substrate are provided herein. In some embodiments, a warpage detector for detecting warpage in substrates...
2018/0323094 CHUCK STAGE PARTICLE DETECTION DEVICE
A particle detection device includes a chuck stage on which a wafer is configured to be seated, first and second adsorption holes shaped as closed concentric...
2018/0323093 INTEGRATED SUBSTRATE TEMPERATURE MEASUREMENT ON HIGH TEMPERATURE CERAMIC HEATER
Embodiments described herein include integrated systems used to directly monitor a substrate temperature during a plasma enhanced deposition process and...
2018/0323092 FLUORESCENCE BASED THERMOMETRY FOR PACKAGING APPLICATIONS
Methods and apparatus for measuring the temperature of epoxy resin in an electronics package are provided herein. In some embodiments, apparatus for...
2018/0323091 METHOD AND APPARATUS FOR UNIFORM THERMAL DISTRIBUTION IN A MICROWAVE CAVITY DURING SEMICONDUCTOR PROCESSING
Methods and apparatus for uniform thermal distribution across semiconductor batches are provided herein. According to one embodiment, a microwave oven for...
2018/0323090 MEDICAL INSTRUMENT FOR IN VIVO HEAT SOURCE
A biocompatible medical device can be at least partially implantable into a living human or animal subject to provide active treatment of biofilm that can...
2018/0323089 BONDING APPARATUS AND BONDING METHOD
A local deformation which is generated on bonded substrates can be reduced. A bonding apparatus includes a first holding unit configured to attract and hold a...
2018/0323088 DIE PLACEMENT HEAD WITH TURRET
Herein described is a system for the placement of dies on a substrate that uses a rotating turret carried with the die placement system to supply die placement...
2018/0323087 HIGH-THROUGHPUT BATCH POROUS SILICON MANUFACTURING EQUIPMENT DESIGN AND PROCESSING METHODS
This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous...
2018/0323086 ROBOT TRANSPORT DEVICE
Gas is circulated in an entire transportation space. A robot transport device includes a transportation space in which a transport robot is provided and...
2018/0323085 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD FOR DISCHARGE OF PROCESSING LIQUID FROM NOZZLE
An upper processing liquid nozzle moves back and forth between a processing position above a substrate held on a spin chuck and a standby position outside a...
2018/0323084 FIRST PROTECTIVE FILM-FORMING SHEET, METHOD FOR FORMING FIRST PROTECTIVE FILM, AND METHOD FOR MANUFACTURING...
The present invention relates to a first protective film-forming sheet formed by stacking a first pressure-sensitive adhesive layer on a first base material...
2018/0323083 Sensor Device With Media Channel Between Substrates
A sensor device including: a first substrate having a bottom surface and a top surface; a second substrate having a bottom surface and a top surface, a media...
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