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Patent # Description
2019/0164914 Seal Ring for Hybrid-Bond
A structure includes a first die and a second die. The first die includes a first oxide bonding layer having a first plurality of bond pads disposed therein...
2019/0164913 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element, an insulated substrate on which the semiconductor element is located, and an external connection...
2019/0164912 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor structure including a first insulation, a second insulation over the first insulation, a third insulation over...
2019/0164911 SEAL RING STRUCTURE, SEMICONDUCTOR DIE, AND METHOD FOR DETECTING CRACKS ON SEMICONDUCTOR DIE
A seal ring structure is provided. The seal ring structure includes a seal ring on a semiconductor substrate. The seal ring includes a first interconnect...
2019/0164907 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package includes a die including a first surface and a second surface opposite to the first surface, a warpage control unit disposed over the...
2019/0164905 SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME
A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is...
2019/0164902 PACKAGE ASSEMBLY FOR DIVIDED ELECTROMAGNETIC SHIELDING AND METHOD OF MANUFACTURING SAME
A package assembly for divided electromagnetic shielding includes a substrate, pad groups, chips, a first colloid, an electromagnetic shielding layer, and a...
2019/0164901 ARRAY SUBSTRATE, CHIP ON FILM, AND ALIGNMENT METHOD
Embodiments of the present application provide an array substrate, a chip on film and an alignment method. The array substrate includes a first pin ...
2019/0164900 MARK, METHOD FOR FORMING SAME, AND EXPOSURE APPARATUS
A mark forming method includes: forming recessed portion on a mark formation area of a substrate; coating the recessed portion with a polymer layer containing...
2019/0164899 System and Method for Aligned Stitching
A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first...
2019/0164898 FINFET WITH ETCH-SELECTIVE SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER
In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may...
2019/0164897 HETEROGENEOUS METAL LINE COMPOSITIONS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller...
2019/0164895 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a...
2019/0164892 MODULE AND METHOD FOR PRODUCING A PLURALITY OF MODULES
The present invention relates to a module that has a lower component of a module (1) having a material (3) in which at least one first structural element (4)...
2019/0164890 PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller...
2019/0164885 BEOL INTEGRATION WITH ADVANCED INTERCONNECTS
An alloy liner is located on a diffusion barrier liner and both are present in at least a via portion of a combined via/line opening that is present in an...
2019/0164884 ELECTRONIC COMPONENT AND THREE-TERMINAL CAPACITOR
In an electronic component, a first ground land and a first hot land are provided on a mounting surface of a first substrate. A semiconductor chip is mounted...
2019/0164883 MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL
A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first...
2019/0164881 INTEGRATED CIRCUIT PACKAGE SUBSTRATE
Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a...
2019/0164880 SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SAME AND POWER CONVERSION APPARATUS
A conductive thin-film thinner than the undersurface electrode is provided outside the undersurface electrode on the undersurface of the ceramic substrate and...
2019/0164875 PREMOLDED SUBSTRATE FOR MOUNTING A SEMICONDUCTOR DIE AND A METHOD OF FABRICATION THEREOF
A method of forming a premolded substrate for mounting a semiconductor die, comprising the steps of providing a carrier; forming conductive circuits on the...
2019/0164874 CHIP-ON-FILM SEMICONDUCTOR DEVICE
A chip-on-film semiconductor device includes a translucent insulator film, a first wire group including a plurality of wires on a first surface of the...
2019/0164872 ELECTRONIC DEVICE
An electronic device comprises a semiconductor chip, an accommodating part that accommodates the semiconductor chip, a plurality of terminals that are provided...
2019/0164871 SEMICONDUCTOR PACKAGE STRUCTURE HAVING A HEAT DISSIPATION STRUCTURE
A semiconductor substrate includes a dielectric layer, a heat dissipation structure and a first patterned conductive layer. The dielectric layer has a surface....
2019/0164868 BIPOLAR TRANSISTOR, SEMICONDUCTOR DEVICE, AND BIPOLAR TRANSISTOR MANUFACTURING METHOD
Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor...
2019/0164867 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor...
2019/0164865 Semiconductor Package
A semiconductor package (1, 1', 1''), the package (1, 1', 1'') comprising a first substrate (2) comprising at a front cavity side (5') a plurality of cavities...
2019/0164864 MULTIPART LID FOR A SEMICONDUCTOR PACKAGE WITH MULTIPLE COMPONENTS
A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed...
2019/0164862 FAN-OUT SEMICONDUCTOR PACKAGE
A semiconductor package includes: a core member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having...
2019/0164861 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME
An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality...
2019/0164859 SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package device includes a substrate, an electronic component, a bonding wire, a heat spreader, a thermal conductive structure and an...
2019/0164858 SEMICONDUCTOR APPARATUS AND ELECTRIC POWER CONVERSION APPARATUS
A semiconductor apparatus includes a base plate, an adhesive agent provided on an upper face of the base plate, and a casing having a lower face and an...
2019/0164853 METHOD FOR INSPECTING SENSOR PACKAGE STRUCTURE, INSPECTION APPARATUS, AND FOCUS ASSISTANT LOADER OF INSPECTION...
An inspection apparatus includes a focus assistant loader and a camera assembly. The focus assistant loader includes a fetching member and a focus member...
2019/0164850 SEMICONDUCTOR STRUCTURE AND TESTING METHOD THEREOF
A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric...
2019/0164844 SEMICONDUCTOR STRUCTURE CUTTING PROCESS AND STRUCTURES FORMED THEREBY
Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the...
2019/0164839 Residue-Free Metal Gate Cutting For Fin-Like Field Effect Transistor
Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated...
2019/0164838 SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF
A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric...
2019/0164835 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a...
2019/0164834 METHODS TO PRODUCE A 3D SEMICONDUCTOR MEMORY DEVICE AND SYSTEM
A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer; forming at least one second level...
2019/0164833 LASER PROCESSING METHOD FOR WAFER
A laser processing method for a wafer includes: linearly forming a plurality of shield tunnels each having a fine hole and an amorphous region surrounding the...
2019/0164829 Semiconductor Device and Method of Manufacture
A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a...
2019/0164828 SEMICONDUCTOR DEVICE, INTERCONNECTION STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor device is provided. The semiconductor device includes a source/drain region, a silicide layer on the source/drain region, an interlayer...
2019/0164825 PHYSICAL VAPOR DEPOSITION PROCESS FOR SEMICONDUCTOR INTERCONNECTION STRUCTURES
The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In...
2019/0164823 CONDUCTIVE FEATURE FORMATION AND STRUCTURE
Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for...
2019/0164822 Semiconductor Device With TiN Adhesion Layer For Forming A Contact Plug
The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through...
2019/0164820 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor structure is provided. The method includes following steps. A MEOL structure is formed on an etch stop layer. A...
2019/0164819 LINER STRUCTURE IN INTERLAYER DIELECTRIC STRUCTURE FOR SEMICONDUCTOR DEVICES
Semiconductor device structures having a liner layer in an interlayer dielectric structure are provided. In one example, a semiconductor device includes an...
2019/0164817 Contact Plugs for Semiconductor Device and Method of Forming Same
A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial...
2019/0164816 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a second layer. The method includes forming a...
2019/0164814 PLUGS FOR INTERCONNECT LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller...
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