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Patent # Description
2019/0172834 SINGLE POLY NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND SINGLE POLY NON-VOLATILE MEMORY...
A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type...
2019/0172833 Integrated Circuitry And 3D Memory
Integrated circuitry has an array circuitry region having a repeating array of electronic components. An adjacent circuitry region is immediately laterally...
2019/0172832 FINFET SRAM LAYOUT AND METHOD OF MAKING THE SAME
A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate...
2019/0172831 LAYOUT OF SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
A layout of semiconductor structure includes plural patterns arranged along a first direction to form plural columns, with each pattern spaced from each other....
2019/0172830 Techniques for Enhancing Vertical Gate-All-Around FET Performance
Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming...
2019/0172829 SEMICONDUCTOR DEVICE FOR TESTING CHARACTERISTICS OF TRANSISTORS AND METHOD FOR TESTING SEMICONDUCTOR DEVICE
A semiconductor device for evaluating characteristics of a transistor is provided. The semiconductor device includes a substrate, an active area defined on the...
2019/0172828 SEMICONDUCTOR APPARATUS HAVING STACKED GATES AND METHOD OF MANUFACTURE THEREOF
Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first...
2019/0172827 EPITAXIAL OXIDE FIN SEGMENTS TO PREVENT STRAINED SEMICONDUCTOR FIN END RELAXATION
A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein...
2019/0172826 A 3D SEMICONDUCTOR WAFER, DEVICES, AND STRUCTURE
A 3D semiconductor wafer, the wafer including: a first device, where the first device includes a first level, the first level including first transistors, and...
2019/0172825 Strapping Structure of Memory Circuit
A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping...
2019/0172824 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first...
2019/0172823 PLACEMENT METHODOLOGY TO REMOVE FILLER
In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure...
2019/0172822 LOGIC LAYOUT WITH REDUCED AREA AND METHOD OF MAKING THE SAME
A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect...
2019/0172821 IN-PACKAGE PHOTONICS INTEGRATION AND ASSEMBLY ARCHITECTURE
In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled...
2019/0172820 DATA STORAGE SYSTEM USING WAFER-LEVEL PACKAGING
A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed...
2019/0172819 LIGHT EMITTING DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME
A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode...
2019/0172818 METHOD OF FORMING PACKAGE STRUCTURE
A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a...
2019/0172817 APPARATUSES AND METHODS FOR SEMICONDUCTOR DIE HEAT DISSIPATION
Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a...
2019/0172816 SEMICONDUCTOR PACKAGE INCLUDING HEAT SINK
A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least...
2019/0172815 Package-in-Package Structure for Semiconductor Devices and Methods of Manufacture
A semiconductor package includes a second leadframe assembly stacked above a first leadframe assembly, each leadframe assembly including a die pad, a plurality...
2019/0172814 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING SIDE MOLDING
Provided is a method of manufacturing a semiconductor package, the method including forming sawing grooves by sawing a wafer along individual chip boundaries...
2019/0172813 SUBSTRATE JOINING METHOD
Provided is a substrate bonding method for bonding a first substrate (11) and a second substrate (12) by sputter-etching, the substrate bonding method...
2019/0172812 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
An electrode is disposed on a semiconductor layer. A polyimide layer has an opening disposed on the electrode, covers the edge of the electrode, and extends...
2019/0172811 Line-integrated switch and method for producing a line-integrated switch
Line-integrated switch having at least a first metal flat part 2, at least a second metal flat part 8, wherein the flat parts are arranged in an overlapping...
2019/0172810 JOINED STRUCTURE, JOINING METHOD, AND JOINING MATERIAL
A joined structure includes: a first member; and a second member that faces the first member and that is joined to the first member via a joining layer. The...
2019/0172809 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a connection member including an insulating layer, a redistribution layer, and conductive vias penetrating through the...
2019/0172808 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a...
2019/0172807 SEMICONDUCTOR APPARATUS
A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An...
2019/0172806 SEMICONDUCTOR ELEMENT
A transistor includes a semiconductor region provided on a substrate and three different terminal electrodes. At least one terminal electrode has an isolated...
2019/0172805 CHIP PACKAGES AND METHODS FOR FORMING THE SAME
A chip package for optical sensing includes a substrate, and a semiconductor device positioned on the substrate and coupled to the substrate through a first...
2019/0172804 Integrated Passive Device for RF Power Amplifier Package
The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising...
2019/0172802 FAN-OUT ANTENNA PACKAGING STRUCTURE AND PREPARATION THEREOF
A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna...
2019/0172801 DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY
Provided are a device and method for generating an identification key using process variation during a bipolar junction transistor (BJT) process. A BJT may be...
2019/0172800 SENSOR AND HEATER FOR STIMULUS-INITIATED FRACTURE OF A SUBSTRATE
A self-destructing device includes a stressed substrate with a heater thermally coupled to the stressed substrate. The device includes a power source and...
2019/0172799 DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY
Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for...
2019/0172798 INTEGRATED CIRCUIT SECURITY
Verifying a semiconductor product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been...
2019/0172797 DISPLAY SUBSTRATE, METHOD OF MANUFACTURING DISPLAY SUBSTRATE, AND DISPLAY DEVICE
There is provided a display substrate, a method of manufacturing a display substrate, and a display device. The display substrate includes a base substrate, a...
2019/0172796 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a...
2019/0172795 CRACK SENSOR FOR SENSING CRACKS IN A SOLDER PAD, AND METHOD FOR PRODUCTION QUALITY CONTROL
An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first...
2019/0172794 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall...
2019/0172793 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface...
2019/0172792 SEMICONDUCTOR PACKAGES
A semiconductor package and a method of fabricating the same, the method including mounting semiconductor chips on a substrate; forming a mold layer that...
2019/0172791 ELECTRONIC CIRCUIT PACKAGE USING CONDUCTIVE SEALING MATERIAL
Disclosed herein is an electronic circuit package that includes a substrate having a power supply pattern, an electronic component mounted on a surface of the...
2019/0172790 DISPLAY DEVICE
A display device includes a window combined with a substrate. The substrate includes a display region with pixels and a non-display region with power lines for...
2019/0172789 SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION
An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor...
2019/0172788 SEMICONDUCTOR MODULE
A semiconductor module includes a substrate, two bare chips (semiconductor elements) mounted on the substrate, and a case fixed to the substrate. A conductor...
2019/0172787 HIGH-DENSITY CHIP-TO-CHIP INTERCONNECTION WITH SILICON BRIDGE
A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies...
2019/0172786 STACK OF LAYERS FOR PROTECTING AGAINST A PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS WITHIN AN...
A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization...
2019/0172785 Integrated Circuit Comprising an Antifuse Structure and Method of Realizing
An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization...
2019/0172784 MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR PACKAGE INTERCONNECT
An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a...
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