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Patent # Description
2019/0172783 CAPACITANCE REDUCTION IN SEA OF LINES BEOL METALLIZATION
A semiconductor interconnect structure and a method of fabricating the same are provided. The semiconductor interconnect structure includes a sea of...
2019/0172782 PACKAGING SUBSTRATE FOR SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND METHOD
A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second...
2019/0172781 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers disposed on the insulating layers, and connection via layers...
2019/0172780 THROUGH-HOLE ELECTRODE SUBSTRATE
A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a...
2019/0172779 Semiconductor Chip Comprising a Multiplicity of External Contacts, Chip Arrangement and Method for Checking an...
A semiconductor chip includes a mounting surface having a plurality of first conductive contacts and at least one second conductive contact. Each of the first...
2019/0172778 HIGH DENSITY PACKAGE INTERCONNECTS
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die...
2019/0172777 LEAD-FRAME STRUCTURE, LEAD-FRAME, SURFACE MOUNT ELECTRONIC DEVICE AND METHODS OF PRODUCING SAME
A lead-frame structure having two faces and exposing a treated silver surface on at least one of said two faces, the treated silver surface(s) serving the wire...
2019/0172776 Method Of Making A Wire Support Leadframe For A Semiconductor Device
A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of...
2019/0172775 FLEXIBLE SUBSTRATE AND ELECTRONIC DEVICE
A flexible substrate according to the present invention comprises a first resin layer, a first wiring layer that is arranged on the first resin layer, a second...
2019/0172774 RECESSED LEAD LEADFRAME PACKAGES
Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads...
2019/0172773 SEMICONDUCTOR APPARATUS
A wiring is disposed above operating regions of plural unit transistors arranged on a substrate in a first direction. An insulating film is disposed on the...
2019/0172772 POWER MODULE SEMICONDUCTOR DEVICE AND INVERTER EQUIPMENT, AND FABRICATION METHOD OF THE POWER MODULE...
The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a...
2019/0172771 LDMOS Transistor
In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a lateral transistor arranged in the front surface of the...
2019/0172770 Semiconductor Device with Integrated pn Diode Temperature Sensor
A semiconductor device includes a semiconductor substrate having a first region with one or more transistor cells and a second region devoid of transistor...
2019/0172769 SEMICONDUCTOR DIE WITH IMPROVED RUGGEDNESS
A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the...
2019/0172768 ACTIVE ESTER RESIN AND CURED PRODUCT THEREOF
Provided are an active ester resin capable of having low cure shrinkage and forming a cured product having a low dielectric loss tangent, a curable resin...
2019/0172767 APPARATUS AND MECHANISMS FOR REDUCING WARPAGE AND INCREASING SURFACE MOUNT TECHNOLOGY YIELDS IN HIGH...
A stiffener apparatus for reducing warpage of an integrated circuit package during heating and cooling are provided. The stiffener apparatus includes an IC...
2019/0172766 SEMICONDUCTOR PACKAGE WITH A WIRE BOND MESH
A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically...
2019/0172765 CIRCUIT BOARD AND SEMICONDUCTOR MODULE
A circuit board includes: a ceramic substrate that has a first surface and a second surface; a first metal part that has a first metal plate joined to the...
2019/0172764 INTEGRATED CHIP SCALE PACKAGES
Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
2019/0172763 SEMICONDUCTOR DEVICE INCLUDING SENSOR AND DRIVING TERMINALS SPACED AWAY FROM THE SEMICONDUCTOR DEVICE CASE WALL
A semiconductor device comprises a power device, a sensor which measures a physical state of the power device to transmit a signal according to the physical...
2019/0172762 METHOD OF INTEGRATED CIRCUIT (IC) CHIP FABRICATION
A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE)....
2019/0172761 PIXEL STRUCTURE
A pixel structure includes at least one sub-pixel. The sub-pixel includes a substrate, a first micro light-emitting element, a repair micro light-emitting...
2019/0172760 MICRO LIGHTING DEVICE
A micro lighting device includes a source line, a ground line, a main LED, and a redundant LED. The main LED includes a first electrode and a second electrode,...
2019/0172759 METHOD OF DETECTING A POSSIBLE THINNING OF A SUBSTRATE OF AN INTEGRATED CIRCUIT VIA THE REAR FACE THEREOF, AND...
A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor...
2019/0172758 EVALUATION METHOD AND MANUFACTURING METHOD OF SiC EPITAXIAL WAFER
An evaluation method of a SiC epitaxial wafer includes: a first observation step of preparing a SiC epitaxial wafer having a high-concentration epitaxial layer...
2019/0172757 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor device according to the present invention includes a manufacturing step of forming a plurality of unit regions each...
2019/0172756 HYBRID HIGH-VOLTAGE LOW-VOLTAGE FINFET DEVICE
An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET...
2019/0172755 METHOD FOR INCORPORATING MULTIPLE CHANNEL MATERIALS IN A COMPLIMENTARY FIELD EFFECTIVE TRANSISTOR (CFET) DEVICE
A method of manufacturing a semiconductor device includes: providing a substrate having a base fin structure thereon, the base fin structure including a first...
2019/0172754 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A fabrication method for a semiconductor device is provided. The method includes: forming a semiconductor substrate including a first region and a second...
2019/0172753 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second...
2019/0172752 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an...
2019/0172751 METHOD FOR CONTROLLING TRANSISTOR DELAY OF NANOWIRE OR NANOSHEET TRANSISTOR DEVICES
A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first...
2019/0172750 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device that enable prevention of generation of tape...
2019/0172749 WAFER PROCESSING METHOD
A wafer is divided along a plurality of division lines by applying a laser beam of such a wavelength as to be transmitted through the wafer, to form division...
2019/0172748 FORMING SELF-ALIGNED VIAS AND AIR-GAPS IN SEMICONDUCTOR FABRICATION
A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a...
2019/0172747 MODULATING THE MICROSTRUCTURE OF METALLIC INTERCONNECT STRUCTURES
Tooling apparatus and methods are provided to fabricate semiconductor devices in which controlled thermal annealing techniques are utilized to modulate...
2019/0172746 SUBSTRATE TRANSPORT APPARATUS
A substrate transport apparatus including a frame, an upper arm rotatably mounted to the frame about a shoulder axis, a forearm rotatably mounted to the upper...
2019/0172745 SUCTION DEVICE, CARRY-IN METHOD, CARRIER SYSTEM AND EXPOSURE APPARATUS, AND DEVICE MANUFACTURING METHOD
In a carrier system, a chuck unit is used to hold a placed wafer from above, and vertical-motion pins use suction to hold the wafer from below. Then, the chuck...
2019/0172743 METHOD TO PROVIDE CONSISTENT ELECTROSTATIC CLAMPING THROUGH REAL TIME CONTROL OF ELECTROSTATIC CHARGE...
An electrostatic clamp monitoring system has an electrostatic clamp configured to selectively electrostatically clamp a workpiece to a clamping surface...
2019/0172742 TEACHING METHOD
In a teaching method for a transfer mechanism that transfers a substrate to a mounting table, the method includes: transferring an inspection substrate having...
2019/0172741 SUBSTRATE TREATMENT APPARATUS, METHOD FOR INSTALLING SUBSTRATE TREATMENT APPARATUS, AND COMPUTER STORAGE MEDIUM
A substrate treatment apparatus for treating a substrate, the substrate treatment apparatus includes: an apparatus main body configured to perform a...
2019/0172740 MODULAR PRESSING DEVICE CAPABLE OF GENERATING STAGE DOWNWARD FORCES AND ELECTRONIC DEVICE TESTING APPARATUS...
A modular pressing device capable of generating stage downward forces is provided. The modular pressing device comprises a non-exchangeable pressing module and...
2019/0172739 SEMICONDUCTOR WAFER PLACEMENT POSITION DETERMINATION METHOD AND SEMICONDUCTOR EPITAXIAL WAFER PRODUCTION METHOD
Provided is a semiconductor wafer placement position determination method making it possible to measure a position deviation at a placement position of a...
2019/0172738 AUTO-CALIBRATION TO A STATION OF A PROCESS MODULE THAT SPINS A WAFER
A method for calibration including determining a temperature induced offset in a pedestal of a process module under a temperature condition for a process. The...
2019/0172737 FUME DETERMINATION METHOD, SUBSTRATE PROCESSING METHOD, AND SUBSTRATE PROCESSING EQUIPMENT
In equipment that supplies a processing liquid on a top surface of a substrate while holding the substrate horizontally in a chamber a generation status of...
2019/0172736 APPARATUS AND METHOD FOR SECURING COMPONENTS OF AN INTEGRATED CIRCUIT
Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated...
2019/0172735 APPARATUS AND METHOD FOR PROCESSING WAFER
A method includes delivering a wafer into a process chamber, applying a thermal energy to the wafer by a heat source, and moving the heat source substantially...
2019/0172734 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
Substrates can be suppressed from being separated from supporting grooves. A substrate processing apparatus includes a substrate holding unit and a processing...
2019/0172733 SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS
A substrate processing method includes a first processing liquid supplying step of supplying a first processing liquid to an upper surface of a substrate, a...
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