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| Patent # | Description |
|---|---|
| US-5,410,704 |
Table modifiable edit functions with order-effective edit rules In a data processing system in which data is entered and validated, a method for performing edit procedures, according to which edit procedures are associated... |
| US-5,410,703 |
System for changing software during computer operation In telecommunications switching system, software is frequently modified, enhanced or replaced altogether by new versions. The implementation or integration of... |
| US-5,410,702 |
Slot objects for an object oriented programming system Data may be manipulated directly in an object oriented programming system by providing a slot object which contains data within its frame. In contrast with... |
| US-5,410,701 |
System and method for analyzing programmed equations A system for the automated analysis of programmed statements, that define parameters and that define equations involving the parameters, includes a method for... |
| US-5,410,700 |
Computer system which supports asynchronous commitment of data A computer system for processing and committing data comprises a processor, an external storage device such as DASD or tape coupled to the processor, and a... |
| US-5,410,699 |
Apparatus and method for loading BIOS from a diskette in a personal
computer system An apparatus and method for loading BIOS from a diskette drive into a personal computer system normally connected to a hardfile, such as a fixed disk. The... |
| US-5,410,698 |
Method and system for dynamic loading of software libraries A method and system for loading a library requested by a service requester of an application program in a computer system. The service requester issues a request... |
| US-5,410,697 |
Concurrency management using version identification of shared data as a
supplement to use of locks A method for managing concurrency using a serializing token as a supplement to locks for accessing the same page by different processes and ensuring coherence... |
| US-5,410,696 |
Method of processing a program by parallel processing, and a processing
unit thereof In order to process a program by parallel processing using a plurality of processors, the program is divided into a plurality of partial programs. Then one or... |
| US-5,410,695 |
Apparatus and method for list management in a coupled data processing
system A Structured External Storage (SES) Facility is coupled to one or more Central Electronic Complex (CEC) Processors, each linked to each other in a System... |
| US-5,410,694 |
File access processing system of a computer enabling high-speed
sequential access for a stream file In a file access processing system for executing sequential access for a copied file in a data processing device which includes a data processing unit and an... |
| US-5,410,693 |
Method and apparatus for accessing a database A method and apparatus for improving the efficiency and security of a database management system (DBMS) is disclosed. A plurality of query packages are stored at... |
| US-5,410,692 |
Method for enhancing interactive query of a database A data processing system has access to a memory storing a data or other information base. The data processing system evaluates objects from the data base against... |
| US-5,410,691 |
Method and apparatus for providing a network configuration database A network database. The network database is arranged in a plurality of domains in a logical hierarchy. Each domain of the hierarchy represents a body of... |
| US-5,410,690 |
System for issuing portable storage media containing common and
individual data An IC card issue system of the present invention issues IC cards, each having a data memory and a control element, to individuals by respectively writing, in the... |
| US-5,410,689 |
System for merge sorting that assigns an optical memory capacity to
concurrent sort cells According to this invention, an address converter for defining a start address of an external memory for each of sort controllers is arranged to each of sort... |
| US-5,410,688 |
Distributed object based systems for communicating object data among
different storage domains An object based data processing system comprising a plurality of storage domains arranged so that a semantic object in a second storage domain can be accessed by... |
| US-5,410,687 |
Analyzing device for saving semiconductor memory failures A failure analysis of a semiconductor memory compares data written into and out of each cell of the semiconductor memory. When there is a disagreement, a "1" is... |
| US-5,410,686 |
Methods for scan path debugging A scan path debugger isolates and identifies hardware and software faults in a computer system containing scan path logic. A user can readily define what... |
| US-5,410,685 |
Non-intrinsive method and system for recovering the state of a computer
system and non-intrusive debugging... A non-intrusive method and system for recovering the state of a computer system including a memory having first and second matched levels. The first level is... |
| US-5,410,684 |
Log name exchange for recovery of protected resources A computer network comprises first and second computers, each having a recovery facility for recovering a two-phase commit procedure and a recovery log. The log... |
| US-5,410,683 |
Programmable divider exhibiting a 50/50 duty cycle A programmable clock divider in which a system reference clock signal is divided by a programmed integer value. A storage register stores a value equal to the... |
| US-5,410,682 |
In-register data manipulation for unaligned byte write using data shift
in reduced instruction set processor A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data... |
| US-5,410,681 |
Interpreter for performing remote testing of computer systems An interpretive language comprises instructions making up part of the first sequence of instructions (a test "script"). The first language comprises a first set... |
| US-5,410,680 |
Solid state memory device having serial input/output A magnetic media hard disk is emulated in a solid state hard disk having a disk controller, a data buffer, a microcontroller, and a disk emulator section. The... |
| US-5,410,679 |
Method and apparatus for concurrently supporting multiple levels of
keyboard display terminal functionality on... Higher functions terminals and lower function terminals, as well as dual mode terminals that are selectively operated at either functional level, are... |
| US-5,410,678 |
Fault simulator comprising a signal generating circuit implemented by
hardware In a fault simulator for simulating a logic circuit model which is operable in response to first through n-th input pattern signals, a signal generating circuit... |
| US-5,410,677 |
Apparatus for translating data formats starting at an arbitrary byte
position A circuit for translating data in one of a plurality of data formats into data in any of the other of the plurality of the data formats including apparatus for... |
| US-5,410,676 |
Information system using designating areas for retrieving/converting
data and directories of different formats... Data and directories are separated and stored on separate parts of an optical disk. Data and directories are written from magnetic disk storage in a first... |
| US-5,410,675 |
Method of conforming input data to an output data structure and engine
for accomplishing same A method for restructuring input data having a prespecified input data structure with a data management engine, such as a translation engine, which is... |
| US-5,410,674 |
Circuit for controlling data transfer from SCSI disk drive to VME bus A digital data system includes a circuit for controlling data transfer between a byte wide device, such as a SCSI disk drive, to a four byte wide pathway such as... |
| US-5,410,673 |
Method and apparatus for simulating a logic circuit having a plurality
of interconnect logic blocks A computer program-implemented logic circuit simulation receives data describing the configuration of a logic circuit to be simulated, and a library of component... |
| US-5,410,672 |
Apparatus and method for the handling of banded frame buffer overflows A method is provided for handling overflows of data blocks in a system using a banded buffer. A block of data is transferred from a memory to a first band in the... |
| US-5,410,671 |
Data compression/decompression processor A data compression/decompression processor (a single-chip VLSI data compression/decompression engine) for use in applications including but not limited to data... |
| US-5,410,670 |
Accessing system that reduces access times due to transmission delays
and I/O access circuitry in a burst mode... A large burst mode memory accessing system includes N discrete sub-memories and three main I/O ports. Data is stored in the sub-memories so that the sub-memories... |
| US-5,410,669 |
Data processor having a cache memory capable of being used as a linear
ram bank A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache... |
| US-5,410,668 |
Reconfigurable cache memory which can selectively inhibit access to
damaged segments in the cache memory A cache memory system includes a buffer having a plurality of segments storing lines of data in addressable storage locations. A first access path is used for... |
| US-5,410,667 |
Data record copy system for a disk drive array data storage subsystem The disk drive array data storage subsystem maps between virtual and physical data storage devices and schedules the writing of data to these devices. The data... |
| US-5,410,666 |
On-line dumping system and disk sub system A buffer memory capable of storing contents of a plurality of tracks of a disk volume is provided in a disk controller or a disk drive, and in dump processing... |
| US-5,410,665 |
Process controller single memory chip shadowing technique A process and apparatus for shadowing memory uses a single memory chip which is addressable into an address field which is smaller than the memory chip. A... |
| US-5,410,664 |
RAM addressing apparatus with lower power consumption and less noise
generation An address converter that reduces the number of address bit changes between successive sequential addresses is provided to a RAM address bus for a sequentially... |
| US-5,410,663 |
Method and system for cache memory congruence class management in a data
processing system A method and system for cache memory congruence class management in a data processing system. A selected address within a data processing system will typically... |
| US-5,410,662 |
Programmable control of EMS page register addresses A full set of 36 EMS registers is provided for a computer, without using any of the registers located in the 256K to 640K address range of the standard RAM. This... |
| US-5,410,661 |
Character string copying method A fractional data processing is performed until a copy source character string comes to K-byte boundary (e.g., K=8). Then, a series of steps of loading data... |
| US-5,410,660 |
System and method for executing branch on bit set/clear instructions
using microprogramming flow A data processing system (10) executes a branch instruction in a straight line microcode sequence. During execution of the instruction, a control unit (56) is... |
| US-5,410,659 |
Digital processor with instruction memory of reduced storage size A digital processor has a data processing unit having arithmetic/logic operation circuits, an instruction memory for storing an instruction word, and an... |
| US-5,410,658 |
Microprocessor for carrying out a plurality of different microprograms
at the same time and method for... The inventive microprocessor includes a first section which runs a microprogram pertinent to a macroinstruction and a second section which runs microprograms... |
| US-5,410,657 |
Method and system for high speed floating point exception enabled
operation in a multiscalar processor system A method and system are disclosed for implementing floating point exception enabled operation without substantial performance degradation. In a multiscalar... |
| US-5,410,656 |
Work station interfacing means having burst mode capability A work station, including a central processing unit (CPU), first, second and third integrated circuit interface chips, connected to an external bus, memory and... |
| US-5,410,655 |
Intersystem channel paging system having a circuit for executing
synchronous or asynchronous instructions for... An apparatus for intersystem I/O channel paging. The I/O channel through an I/O channel adapter provides communication between a central processor, an I/O... |
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